1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM System MMU Architecture Implementation
8
9maintainers:
10  - Will Deacon <[email protected]>
11  - Robin Murphy <[email protected]>
12
13description: |+
14  ARM SoCs may contain an implementation of the ARM System Memory
15  Management Unit Architecture, which can be used to provide 1 or 2 stages
16  of address translation to bus masters external to the CPU.
17
18  The SMMU may also raise interrupts in response to various fault
19  conditions.
20
21properties:
22  $nodename:
23    pattern: "^iommu@[0-9a-f]*"
24  compatible:
25    oneOf:
26      - description: Qcom SoCs implementing "arm,smmu-v2"
27        items:
28          - enum:
29              - qcom,msm8996-smmu-v2
30              - qcom,msm8998-smmu-v2
31              - qcom,sdm630-smmu-v2
32              - qcom,sm6375-smmu-v2
33          - const: qcom,smmu-v2
34
35      - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500"
36        items:
37          - enum:
38              - qcom,qcm2290-smmu-500
39              - qcom,qcs615-smmu-500
40              - qcom,qcs8300-smmu-500
41              - qcom,qdu1000-smmu-500
42              - qcom,sa8255p-smmu-500
43              - qcom,sa8775p-smmu-500
44              - qcom,sar2130p-smmu-500
45              - qcom,sc7180-smmu-500
46              - qcom,sc7280-smmu-500
47              - qcom,sc8180x-smmu-500
48              - qcom,sc8280xp-smmu-500
49              - qcom,sdm670-smmu-500
50              - qcom,sdm845-smmu-500
51              - qcom,sdx55-smmu-500
52              - qcom,sdx65-smmu-500
53              - qcom,sdx75-smmu-500
54              - qcom,sm6115-smmu-500
55              - qcom,sm6125-smmu-500
56              - qcom,sm6350-smmu-500
57              - qcom,sm6375-smmu-500
58              - qcom,sm8150-smmu-500
59              - qcom,sm8250-smmu-500
60              - qcom,sm8350-smmu-500
61              - qcom,sm8450-smmu-500
62              - qcom,sm8550-smmu-500
63              - qcom,sm8650-smmu-500
64              - qcom,sm8750-smmu-500
65              - qcom,x1e80100-smmu-500
66          - const: qcom,smmu-500
67          - const: arm,mmu-500
68
69      - description: Qcom SoCs implementing "arm,mmu-500" (legacy binding)
70        deprecated: true
71        items:
72          # Do not add additional SoC to this list. Instead use two previous lists.
73          - enum:
74              - qcom,qcm2290-smmu-500
75              - qcom,sc7180-smmu-500
76              - qcom,sc7280-smmu-500
77              - qcom,sc8180x-smmu-500
78              - qcom,sc8280xp-smmu-500
79              - qcom,sdm845-smmu-500
80              - qcom,sm6115-smmu-500
81              - qcom,sm6350-smmu-500
82              - qcom,sm6375-smmu-500
83              - qcom,sm8150-smmu-500
84              - qcom,sm8250-smmu-500
85              - qcom,sm8350-smmu-500
86              - qcom,sm8450-smmu-500
87          - const: arm,mmu-500
88      - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500"
89        items:
90          - enum:
91              - qcom,qcm2290-smmu-500
92              - qcom,qcs615-smmu-500
93              - qcom,sa8255p-smmu-500
94              - qcom,sa8775p-smmu-500
95              - qcom,sar2130p-smmu-500
96              - qcom,sc7280-smmu-500
97              - qcom,sc8180x-smmu-500
98              - qcom,sc8280xp-smmu-500
99              - qcom,sm6115-smmu-500
100              - qcom,sm6125-smmu-500
101              - qcom,sm8150-smmu-500
102              - qcom,sm8250-smmu-500
103              - qcom,sm8350-smmu-500
104              - qcom,sm8450-smmu-500
105              - qcom,sm8550-smmu-500
106              - qcom,sm8650-smmu-500
107              - qcom,sm8750-smmu-500
108              - qcom,x1e80100-smmu-500
109          - const: qcom,adreno-smmu
110          - const: qcom,smmu-500
111          - const: arm,mmu-500
112      - description: Qcom Adreno GPUs implementing "arm,mmu-500" (legacy binding)
113        deprecated: true
114        items:
115          # Do not add additional SoC to this list. Instead use previous list.
116          - enum:
117              - qcom,sc7280-smmu-500
118              - qcom,sm8150-smmu-500
119              - qcom,sm8250-smmu-500
120          - const: qcom,adreno-smmu
121          - const: arm,mmu-500
122      - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
123        items:
124          - enum:
125              - qcom,msm8996-smmu-v2
126              - qcom,sc7180-smmu-v2
127              - qcom,sdm630-smmu-v2
128              - qcom,sdm670-smmu-v2
129              - qcom,sdm845-smmu-v2
130              - qcom,sm6350-smmu-v2
131              - qcom,sm7150-smmu-v2
132          - const: qcom,adreno-smmu
133          - const: qcom,smmu-v2
134      - description: Qcom Adreno GPUs on Google Cheza platform
135        items:
136          - const: qcom,sdm845-smmu-v2
137          - const: qcom,smmu-v2
138      - description: Marvell SoCs implementing "arm,mmu-500"
139        items:
140          - const: marvell,ap806-smmu-500
141          - const: arm,mmu-500
142      - description: NVIDIA SoCs that require memory controller interaction
143          and may program multiple ARM MMU-500s identically with the memory
144          controller interleaving translations between multiple instances
145          for improved performance.
146        items:
147          - enum:
148              - nvidia,tegra186-smmu
149              - nvidia,tegra194-smmu
150              - nvidia,tegra234-smmu
151          - const: nvidia,smmu-500
152      - items:
153          - const: arm,mmu-500
154          - const: arm,smmu-v2
155      - items:
156          - enum:
157              - arm,mmu-400
158              - arm,mmu-401
159          - const: arm,smmu-v1
160      - enum:
161          - arm,smmu-v1
162          - arm,smmu-v2
163          - arm,mmu-400
164          - arm,mmu-401
165          - arm,mmu-500
166          - cavium,smmu-v2
167
168  reg:
169    minItems: 1
170    maxItems: 2
171
172  '#global-interrupts':
173    description: The number of global interrupts exposed by the device.
174    $ref: /schemas/types.yaml#/definitions/uint32
175    minimum: 0
176    maximum: 260   # 2 secure, 2 non-secure, and up to 256 perf counters
177
178  '#iommu-cells':
179    enum: [ 1, 2 ]
180    description: |
181      See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a
182      value of 1, each IOMMU specifier represents a distinct stream ID emitted
183      by that device into the relevant SMMU.
184
185      SMMUs with stream matching support and complex masters may use a value of
186      2, where the second cell of the IOMMU specifier represents an SMR mask to
187      combine with the ID in the first cell.  Care must be taken to ensure the
188      set of matched IDs does not result in conflicts.
189
190  interrupts:
191    minItems: 1
192    maxItems: 388   # 260 plus 128 contexts
193    description: |
194      Interrupt list, with the first #global-interrupts entries corresponding to
195      the global interrupts and any following entries corresponding to context
196      interrupts, specified in order of their indexing by the SMMU.
197
198      For SMMUv2 implementations, there must be exactly one interrupt per
199      context bank. In the case of a single, combined interrupt, it must be
200      listed multiple times.
201
202  dma-coherent:
203    description: |
204      Present if page table walks made by the SMMU are cache coherent with the
205      CPU.
206
207      NOTE: this only applies to the SMMU itself, not masters connected
208      upstream of the SMMU.
209
210  calxeda,smmu-secure-config-access:
211    type: boolean
212    description:
213      Enable proper handling of buggy implementations that always use secure
214      access to SMMU configuration registers. In this case non-secure aliases of
215      secure registers have to be used during SMMU configuration.
216
217  stream-match-mask:
218    $ref: /schemas/types.yaml#/definitions/uint32
219    description: |
220      For SMMUs supporting stream matching and using #iommu-cells = <1>,
221      specifies a mask of bits to ignore when matching stream IDs (e.g. this may
222      be programmed into the SMRn.MASK field of every stream match register
223      used). For cases where it is desirable to ignore some portion of every
224      Stream ID (e.g. for certain MMU-500 configurations given globally unique
225      input IDs). This property is not valid for SMMUs using stream indexing, or
226      using stream matching with #iommu-cells = <2>, and may be ignored if
227      present in such cases.
228
229  clock-names:
230    minItems: 1
231    maxItems: 7
232
233  clocks:
234    minItems: 1
235    maxItems: 7
236
237  power-domains:
238    minItems: 1
239    maxItems: 3
240
241  nvidia,memory-controller:
242    description: |
243      A phandle to the memory controller on NVIDIA Tegra186 and later SoCs.
244      The memory controller needs to be programmed with a mapping of memory
245      client IDs to ARM SMMU stream IDs.
246
247      If this property is absent, the mapping programmed by early firmware
248      will be used and it is not guaranteed that IOMMU translations will be
249      enabled for any given device.
250    $ref: /schemas/types.yaml#/definitions/phandle
251
252required:
253  - compatible
254  - reg
255  - '#global-interrupts'
256  - '#iommu-cells'
257  - interrupts
258
259additionalProperties: false
260
261allOf:
262  - if:
263      properties:
264        compatible:
265          contains:
266            enum:
267              - nvidia,tegra186-smmu
268              - nvidia,tegra194-smmu
269              - nvidia,tegra234-smmu
270    then:
271      properties:
272        reg:
273          minItems: 1
274          maxItems: 2
275
276      # The reference to the memory controller is required to ensure that the
277      # memory client to stream ID mapping can be done synchronously with the
278      # IOMMU attachment.
279      required:
280        - nvidia,memory-controller
281    else:
282      properties:
283        reg:
284          maxItems: 1
285
286  - if:
287      properties:
288        compatible:
289          contains:
290            enum:
291              - qcom,msm8998-smmu-v2
292              - qcom,sdm630-smmu-v2
293    then:
294      anyOf:
295        - properties:
296            clock-names:
297              items:
298                - const: bus
299            clocks:
300              items:
301                - description: bus clock required for downstream bus access and for
302                    the smmu ptw
303        - properties:
304            clock-names:
305              items:
306                - const: iface
307                - const: mem
308                - const: mem_iface
309            clocks:
310              items:
311                - description: interface clock required to access smmu's registers
312                    through the TCU's programming interface.
313                - description: bus clock required for memory access
314                - description: bus clock required for GPU memory access
315        - properties:
316            clock-names:
317              items:
318                - const: iface-mm
319                - const: iface-smmu
320                - const: bus-smmu
321            clocks:
322              items:
323                - description: interface clock required to access mnoc's registers
324                    through the TCU's programming interface.
325                - description: interface clock required to access smmu's registers
326                    through the TCU's programming interface.
327                - description: bus clock required for the smmu ptw
328
329  - if:
330      properties:
331        compatible:
332          contains:
333            enum:
334              - qcom,sm6375-smmu-v2
335    then:
336      anyOf:
337        - properties:
338            clock-names:
339              items:
340                - const: bus
341            clocks:
342              items:
343                - description: bus clock required for downstream bus access and for
344                    the smmu ptw
345        - properties:
346            clock-names:
347              items:
348                - const: iface
349                - const: mem
350                - const: mem_iface
351            clocks:
352              items:
353                - description: interface clock required to access smmu's registers
354                    through the TCU's programming interface.
355                - description: bus clock required for memory access
356                - description: bus clock required for GPU memory access
357        - properties:
358            clock-names:
359              items:
360                - const: iface-mm
361                - const: iface-smmu
362                - const: bus-mm
363                - const: bus-smmu
364            clocks:
365              items:
366                - description: interface clock required to access mnoc's registers
367                    through the TCU's programming interface.
368                - description: interface clock required to access smmu's registers
369                    through the TCU's programming interface.
370                - description: bus clock required for downstream bus access
371                - description: bus clock required for the smmu ptw
372
373  - if:
374      properties:
375        compatible:
376          contains:
377            enum:
378              - qcom,msm8996-smmu-v2
379              - qcom,sc7180-smmu-v2
380              - qcom,sdm845-smmu-v2
381    then:
382      properties:
383        clock-names:
384          items:
385            - const: bus
386            - const: iface
387
388        clocks:
389          items:
390            - description: bus clock required for downstream bus access and for
391                the smmu ptw
392            - description: interface clock required to access smmu's registers
393                through the TCU's programming interface.
394
395  - if:
396      properties:
397        compatible:
398          contains:
399            enum:
400              - qcom,sa8775p-smmu-500
401              - qcom,sc7280-smmu-500
402              - qcom,sc8280xp-smmu-500
403    then:
404      properties:
405        clock-names:
406          items:
407            - const: gcc_gpu_memnoc_gfx_clk
408            - const: gcc_gpu_snoc_dvm_gfx_clk
409            - const: gpu_cc_ahb_clk
410            - const: gpu_cc_hlos1_vote_gpu_smmu_clk
411            - const: gpu_cc_cx_gmu_clk
412            - const: gpu_cc_hub_cx_int_clk
413            - const: gpu_cc_hub_aon_clk
414
415        clocks:
416          items:
417            - description: GPU memnoc_gfx clock
418            - description: GPU snoc_dvm_gfx clock
419            - description: GPU ahb clock
420            - description: GPU hlos1_vote_GPU smmu clock
421            - description: GPU cx_gmu clock
422            - description: GPU hub_cx_int clock
423            - description: GPU hub_aon clock
424
425  - if:
426      properties:
427        compatible:
428          contains:
429            enum:
430              - qcom,sc8180x-smmu-500
431              - qcom,sm6350-smmu-v2
432              - qcom,sm7150-smmu-v2
433              - qcom,sm8150-smmu-500
434              - qcom,sm8250-smmu-500
435    then:
436      properties:
437        clock-names:
438          items:
439            - const: ahb
440            - const: bus
441            - const: iface
442
443        clocks:
444          items:
445            - description: bus clock required for AHB bus access
446            - description: bus clock required for downstream bus access and for
447                the smmu ptw
448            - description: interface clock required to access smmu's registers
449                through the TCU's programming interface.
450
451  - if:
452      properties:
453        compatible:
454          items:
455            - enum:
456                - qcom,sm8350-smmu-500
457            - const: qcom,adreno-smmu
458            - const: qcom,smmu-500
459            - const: arm,mmu-500
460    then:
461      properties:
462        clock-names:
463          items:
464            - const: bus
465            - const: iface
466            - const: ahb
467            - const: hlos1_vote_gpu_smmu
468            - const: cx_gmu
469            - const: hub_cx_int
470            - const: hub_aon
471        clocks:
472          minItems: 7
473          maxItems: 7
474
475  - if:
476      properties:
477        compatible:
478          items:
479            - enum:
480                - qcom,qcm2290-smmu-500
481                - qcom,qcs615-smmu-500
482                - qcom,sm6115-smmu-500
483                - qcom,sm6125-smmu-500
484            - const: qcom,adreno-smmu
485            - const: qcom,smmu-500
486            - const: arm,mmu-500
487    then:
488      properties:
489        clock-names:
490          items:
491            - const: mem
492            - const: hlos
493            - const: iface
494
495        clocks:
496          items:
497            - description: GPU memory bus clock
498            - description: Voter clock required for HLOS SMMU access
499            - description: Interface clock required for register access
500
501  - if:
502      properties:
503        compatible:
504          items:
505            - const: qcom,sm8450-smmu-500
506            - const: qcom,adreno-smmu
507            - const: qcom,smmu-500
508            - const: arm,mmu-500
509
510    then:
511      properties:
512        clock-names:
513          items:
514            - const: gmu
515            - const: hub
516            - const: hlos
517            - const: bus
518            - const: iface
519            - const: ahb
520
521        clocks:
522          items:
523            - description: GMU clock
524            - description: GPU HUB clock
525            - description: HLOS vote clock
526            - description: GPU memory bus clock
527            - description: GPU SNoC bus clock
528            - description: GPU AHB clock
529
530  - if:
531      properties:
532        compatible:
533          items:
534            - enum:
535                - qcom,sar2130p-smmu-500
536                - qcom,sm8550-smmu-500
537                - qcom,sm8650-smmu-500
538                - qcom,x1e80100-smmu-500
539            - const: qcom,adreno-smmu
540            - const: qcom,smmu-500
541            - const: arm,mmu-500
542    then:
543      properties:
544        clock-names:
545          items:
546            - const: hlos
547            - const: bus
548            - const: iface
549            - const: ahb
550
551        clocks:
552          items:
553            - description: HLOS vote clock
554            - description: GPU memory bus clock
555            - description: GPU SNoC bus clock
556            - description: GPU AHB clock
557
558  - if:
559      properties:
560        compatible:
561          items:
562            - const: qcom,sm8750-smmu-500
563            - const: qcom,adreno-smmu
564            - const: qcom,smmu-500
565            - const: arm,mmu-500
566    then:
567      properties:
568        clock-names:
569          items:
570            - const: hlos
571        clocks:
572          items:
573            - description: HLOS vote clock
574
575  # Disallow clocks for all other platforms with specific compatibles
576  - if:
577      properties:
578        compatible:
579          contains:
580            enum:
581              - cavium,smmu-v2
582              - marvell,ap806-smmu-500
583              - nvidia,smmu-500
584              - qcom,qcs8300-smmu-500
585              - qcom,qdu1000-smmu-500
586              - qcom,sa8255p-smmu-500
587              - qcom,sc7180-smmu-500
588              - qcom,sdm670-smmu-500
589              - qcom,sdm845-smmu-500
590              - qcom,sdx55-smmu-500
591              - qcom,sdx65-smmu-500
592              - qcom,sm6350-smmu-500
593              - qcom,sm6375-smmu-500
594    then:
595      properties:
596        clock-names: false
597        clocks: false
598
599  - if:
600      properties:
601        compatible:
602          contains:
603            const: qcom,sm6375-smmu-500
604    then:
605      properties:
606        power-domains:
607          items:
608            - description: SNoC MMU TBU RT GDSC
609            - description: SNoC MMU TBU NRT GDSC
610            - description: SNoC TURING MMU TBU0 GDSC
611
612      required:
613        - power-domains
614    else:
615      properties:
616        power-domains:
617          maxItems: 1
618
619examples:
620  - |+
621    /* SMMU with stream matching or stream indexing */
622    smmu1: iommu@ba5e0000 {
623            compatible = "arm,smmu-v1";
624            reg = <0xba5e0000 0x10000>;
625            #global-interrupts = <2>;
626            interrupts = <0 32 4>,
627                         <0 33 4>,
628                         <0 34 4>, /* This is the first context interrupt */
629                         <0 35 4>,
630                         <0 36 4>,
631                         <0 37 4>;
632            #iommu-cells = <1>;
633    };
634
635    /* device with two stream IDs, 0 and 7 */
636    master1 {
637            iommus = <&smmu1 0>,
638                     <&smmu1 7>;
639    };
640
641
642    /* SMMU with stream matching */
643    smmu2: iommu@ba5f0000 {
644            compatible = "arm,smmu-v1";
645            reg = <0xba5f0000 0x10000>;
646            #global-interrupts = <2>;
647            interrupts = <0 38 4>,
648                         <0 39 4>,
649                         <0 40 4>, /* This is the first context interrupt */
650                         <0 41 4>,
651                         <0 42 4>,
652                         <0 43 4>;
653            #iommu-cells = <2>;
654    };
655
656    /* device with stream IDs 0 and 7 */
657    master2 {
658            iommus = <&smmu2 0 0>,
659                     <&smmu2 7 0>;
660    };
661
662    /* device with stream IDs 1, 17, 33 and 49 */
663    master3 {
664            iommus = <&smmu2 1 0x30>;
665    };
666
667
668    /* ARM MMU-500 with 10-bit stream ID input configuration */
669    smmu3: iommu@ba600000 {
670            compatible = "arm,mmu-500", "arm,smmu-v2";
671            reg = <0xba600000 0x10000>;
672            #global-interrupts = <2>;
673            interrupts = <0 44 4>,
674                         <0 45 4>,
675                         <0 46 4>, /* This is the first context interrupt */
676                         <0 47 4>,
677                         <0 48 4>,
678                         <0 49 4>;
679            #iommu-cells = <1>;
680            /* always ignore appended 5-bit TBU number */
681            stream-match-mask = <0x7c00>;
682    };
683
684    bus {
685            /* bus whose child devices emit one unique 10-bit stream
686               ID each, but may master through multiple SMMU TBUs */
687            iommu-map = <0 &smmu3 0 0x400>;
688
689
690    };
691
692  - |+
693    /* Qcom's arm,smmu-v2 implementation */
694    #include <dt-bindings/interrupt-controller/arm-gic.h>
695    #include <dt-bindings/interrupt-controller/irq.h>
696    smmu4: iommu@d00000 {
697      compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
698      reg = <0xd00000 0x10000>;
699
700      #global-interrupts = <1>;
701      interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
702             <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
703             <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
704      #iommu-cells = <1>;
705      power-domains = <&mmcc 0>;
706
707      clocks = <&mmcc 123>,
708        <&mmcc 124>;
709      clock-names = "bus", "iface";
710    };
711