Searched +full:jh8100 +full:- +full:intc (Results 1 – 6 of 6) sorted by relevance
| /linux-6.14.4/drivers/irqchip/ |
| D | irq-starfive-jh8100-intc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * StarFive JH8100 External Interrupt Controller driver
10 #define pr_fmt(fmt) "irq-starfive-jh8100: " fmt
40 value = ioread32(irqc->base + reg); in starfive_intc_bit_set()
42 iowrite32(value, irqc->base + reg); in starfive_intc_bit_set()
50 value = ioread32(irqc->base + reg); in starfive_intc_bit_clear()
52 iowrite32(value, irqc->base + reg); in starfive_intc_bit_clear()
59 raw_spin_lock(&irqc->lock); in starfive_intc_unmask()
60 starfive_intc_bit_clear(irqc, STARFIVE_INTC_SRC0_MASK, BIT(d->hwirq)); in starfive_intc_unmask()
61 raw_spin_unlock(&irqc->lock); in starfive_intc_unmask()
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
119 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
127 tristate "Broadcom STB 7120-style L2 interrupt controller driver"
181 will be called irq-lan966x-oic.
222 bool "J-Core integrated AIC" if COMPILE_TEST
226 Support for the J-Core integrated AIC.
233 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
237 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
240 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
245 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
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| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_IRQCHIP) += irqchip.o
4 obj-$(CONFIG_AL_FIC) += irq-al-fic.o
5 obj-$(CONFIG_ALPINE_MSI) += irq-alpine-msi.o
6 obj-$(CONFIG_ATH79) += irq-ath79-cpu.o
7 obj-$(CONFIG_ATH79) += irq-ath79-misc.o
8 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
9 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
10 obj-$(CONFIG_ARCH_ACTIONS) += irq-owl-sirq.o
11 obj-$(CONFIG_DAVINCI_CP_INTC) += irq-davinci-cp-intc.o
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| /linux-6.14.4/Documentation/devicetree/bindings/interrupt-controller/ |
| D | starfive,jh8100-intc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/starfive,jh8100-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 StarFive SoC JH8100 contain a external interrupt controller. It can be used
11 to handle high-level input interrupt signals. It also send the output
12 interrupt signal to RISC-V PLIC.
15 - Changhuang Liang <[email protected]>
19 const: starfive,jh8100-intc
35 interrupt-controller: true
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| /linux-6.14.4/Documentation/devicetree/bindings/dma/ |
| D | snps,dw-axi-dmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Eugeniy Paltsev <[email protected]>
16 - $ref: dma-controller.yaml#
21 - snps,axi-dma-1.01a
22 - intel,kmb-axi-dma
23 - starfive,jh7110-axi-dma
24 - starfive,jh8100-axi-dma
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| /linux-6.14.4/ |
| D | MAINTAINERS | 5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-[email protected]
88 F: drivers/scsi/3w-*
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