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/linux-6.14.4/Documentation/devicetree/bindings/sound/
Dstarfive,jh7110-pwmdac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/starfive,jh7110-pwmdac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 PWM-DAC Controller
10 The PWM-DAC Controller uses PWM square wave generators plus RC filters to
11 form a DAC for audio play in StarFive JH7110 SoC. This audio play controller
16 - Hal Feng <[email protected]>
19 - $ref: dai-common.yaml#
23 const: starfive,jh7110-pwmdac
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/linux-6.14.4/Documentation/devicetree/bindings/pinctrl/
Dstarfive,jh7110-aon-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-aon-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 AON Pin Controller
10 Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
15 Some peripherals such as PWM have their I/O go through the 4 "GPIOs".
18 - Jianlong Huang <[email protected]>
22 const: starfive,jh7110-aon-pinctrl
33 interrupt-controller: true
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/linux-6.14.4/Documentation/devicetree/bindings/pwm/
Dopencores,pwm.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pwm/opencores,pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: OpenCores PWM controller
10 - William Qiu <[email protected]>
13 The OpenCores PTC ip core contains a PWM controller. When operating in PWM
14 mode, the PTC core generates binary signal with user-programmable low and
15 high periods. All PTC counters and registers are 32-bit.
18 - $ref: pwm.yaml#
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/linux-6.14.4/sound/soc/starfive/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
11 tristate "JH7110 PWM-DAC device driver"
16 Say Y or M if you want to add support for StarFive JH7110
17 PWM-DAC driver.
20 tristate "JH7110 TDM device driver"
Djh7110_pwmdac.c1 // SPDX-License-Identifier: GPL-2.0
3 * jh7110_pwmdac.c -- StarFive JH7110 PWM-DAC driver
5 * Copyright (C) 2021-2023 StarFive Technology Co., Ltd.
115 value = jh7110_pwmdac_read_reg(dev->base, JH7110_PWMDAC_CTRL); in jh7110_pwmdac_set_enable()
121 jh7110_pwmdac_write_reg(dev->base, JH7110_PWMDAC_CTRL, value); in jh7110_pwmdac_set_enable()
128 value = jh7110_pwmdac_read_reg(dev->base, JH7110_PWMDAC_CTRL); in jh7110_pwmdac_set_shift()
129 if (dev->cfg.shift == PWMDAC_SHIFT_8) in jh7110_pwmdac_set_shift()
131 else if (dev->cfg.shift == PWMDAC_SHIFT_10) in jh7110_pwmdac_set_shift()
134 jh7110_pwmdac_write_reg(dev->base, JH7110_PWMDAC_CTRL, value); in jh7110_pwmdac_set_shift()
141 value = jh7110_pwmdac_read_reg(dev->base, JH7110_PWMDAC_CTRL); in jh7110_pwmdac_set_duty_cycle()
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/linux-6.14.4/arch/riscv/boot/dts/starfive/
Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "starfive,jh7110";
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
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Djh7110-milkv-mars.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 /dts-v1/;
7 #include "jh7110-common.dtsi"
10 model = "Milk-V Mars";
11 compatible = "milkv,mars", "starfive,jh7110";
15 starfive,tx-use-rgmii-clk;
16 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
17 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
34 motorcomm,tx-clk-adj-enabled;
35 motorcomm,tx-clk-10-inverted;
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Djh7110-pine64-star64.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 /dts-v1/;
7 #include "jh7110-common.dtsi"
11 compatible = "pine64,star64", "starfive,jh7110";
18 starfive,tx-use-rgmii-clk;
19 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
20 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
25 phy-handle = <&phy1>;
26 phy-mode = "rgmii-id";
27 starfive,tx-use-rgmii-clk;
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Djh7110-starfive-visionfive-2.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include "jh7110-common.dtsi"
21 phy-handle = <&phy1>;
22 phy-mode = "rgmii-id";
26 #address-cells = <1>;
27 #size-cells = <0>;
28 compatible = "snps,dwmac-mdio";
30 phy1: ethernet-phy@1 {
41 non-removable;
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Djh7110-common.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include "jh7110.dtsi"
9 #include "jh7110-pinfunc.h"
10 #include <dt-bindings/gpio/gpio.h>
25 stdout-path = "serial0:115200n8";
33 gpio-restart {
34 compatible = "gpio-restart";
39 pwmdac_codec: audio-codec {
40 compatible = "linux,spdif-dit";
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/linux-6.14.4/drivers/clk/starfive/
Dclk-starfive-jh7110-sys.c1 // SPDX-License-Identifier: GPL-2.0
3 * StarFive JH7110 System Clock Driver
11 #include <linux/clk-provider.h>
17 #include <soc/starfive/reset-starfive-jh71x0.h>
19 #include <dt-bindings/clock/starfive,jh7110-crg.h>
21 #include "clk-starfive-jh7110.h"
216 /* pwm */
352 return -ENOMEM; in jh7110_reset_controller_register()
354 rdev->base = priv->base; in jh7110_reset_controller_register()
356 adev = &rdev->adev; in jh7110_reset_controller_register()
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/linux-6.14.4/
DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-[email protected]
88 F: drivers/scsi/3w-*
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