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/linux-6.14.4/Documentation/devicetree/bindings/iio/adc/
Dadi,ad7625.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <[email protected]>
11 - Nuno Sá <[email protected]>
24 - adi,ad7625
25 - adi,ad7626
26 - adi,ad7960
27 - adi,ad7961
29 vdd1-supply: true
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Dadi,ad7944.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <[email protected]>
11 - Nuno Sá <[email protected]>
14 A family of pin-compatible single channel differential analog to digital
21 $ref: /schemas/spi/spi-peripheral-props.yaml#
26 - adi,ad7944
27 - adi,ad7985
28 - adi,ad7986
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Dadi,ad4000.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marcelo Schmitt <[email protected]>
15 https://www.analog.com/media/en/technical-documentation/data-sheets/ad4000-4004-4008.pdf
16 https://www.analog.com/media/en/technical-documentation/data-sheets/ad4001-4005.pdf
17 https://www.analog.com/media/en/technical-documentation/data-sheets/ad4002-4006-4010.pdf
18 https://www.analog.com/media/en/technical-documentation/data-sheets/ad4003-4007-4011.pdf
19 https://www.analog.com/media/en/technical-documentation/data-sheets/ad4020-4021-4022.pdf
20 https://www.analog.com/media/en/technical-documentation/data-sheets/adaq4001.pdf
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/linux-6.14.4/include/drm/intel/
Di915_hdcp_interface.h1 /* SPDX-License-Identifier: (GPL-2.0+) */
3 * Copyright © 2017-2019 Intel Corporation
17 * enum hdcp_port_type - HDCP port implementation type defined by ME/GSC FW
19 * @HDCP_PORT_TYPE_INTEGRATED: In-Host HDCP2.x port
20 * @HDCP_PORT_TYPE_LSPCON: HDCP2.2 discrete wired Tx port with LSPCON
22 * @HDCP_PORT_TYPE_CPDP: HDCP2.2 discrete wired Tx port using the CPDP (DP 1.3)
33 * enum hdcp_wired_protocol - HDCP adaptation used on the port
57 * enum hdcp_transcoder - ME/GSC Firmware defined index for transcoders
79 * struct hdcp_port_data - intel specific HDCP port data
84 * @k: No of streams transmitted on a port. Only on DP MST this is != 1
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/linux-6.14.4/arch/mips/mm/
Dtlb-r4k.c2 * This file is subject to the terms and conditions of the GNU General Public
20 #include <asm/cpu-type.h>
30 * LOONGSON-2 has a 4 entry itlb which is a subset of jtlb, LOONGSON-3 has
50 if (vma->vm_flags & VM_EXEC) in flush_micro_tlb_vm()
71 * If there are any wired entries, fall back to iterating in local_flush_tlb_all()
109 struct mm_struct *mm = vma->vm_mm; in local_flush_tlb_range()
118 size = (end - start) >> (PAGE_SHIFT + 1); in local_flush_tlb_range()
171 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; in local_flush_tlb_kernel_range()
179 end += ((PAGE_SIZE << 1) - 1); in local_flush_tlb_kernel_range()
215 if (cpu_context(cpu, vma->vm_mm) != 0) { in local_flush_tlb_page()
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Dinit.c2 * This file is subject to the terms and conditions of the GNU General Public
6 * Copyright (C) 1994 - 2000 Ralf Baechle
50 * when needed. This is necessary only on R4000 / R4400 SC and MC versions
52 * any price. Since page is never written to after the initialization we
81 zero_page_mask = ((PAGE_SIZE << order) - 1) & PAGE_MASK; in setup_zero_pages()
97 idx = (addr >> PAGE_SHIFT) & (FIX_N_COLOURS - 1); in __kmap_pgprot()
99 vaddr = __fix_to_virt(FIX_CMAP_END - idx); in __kmap_pgprot()
151 unsigned int wired; in kunmap_coherent() local
156 wired = num_wired_entries() - 1; in kunmap_coherent()
157 write_c0_wired(wired); in kunmap_coherent()
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/linux-6.14.4/Documentation/devicetree/bindings/interrupt-controller/
Dimg,pdc-intc.txt10 - compatible: Specifies the compatibility list for the interrupt controller.
11 The type shall be <string> and the value shall include "img,pdc-intc".
13 - reg: Specifies the base PDC physical address(s) and size(s) of the
14 addressable register space. The type shall be <prop-encoded-array>.
16 - interrupt-controller: The presence of this property identifies the node
19 - #interrupt-cells: Specifies the number of cells needed to encode an
22 - num-perips: Number of waking peripherals.
24 - num-syswakes: Number of SysWake inputs.
26 - interrupts: List of interrupt specifiers. The first specifier shall be the
34 - <1st-cell>: The interrupt-number that identifies the interrupt source.
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Dmarvell,sei.txt2 -----------------------------------------------
4 Marvell SEI (System Error Interrupt) controller is an interrupt
10 AP and is wired while a second set comes from the CPs by the mean of
15 - compatible: should be one of:
16 * "marvell,ap806-sei"
17 - reg: SEI registers location and length.
18 - interrupts: identifies the parent IRQ that will be triggered.
19 - #interrupt-cells: number of cells to define an SEI wired interrupt
20 coming from the AP, should be 1. The cell is the IRQ
22 - interrupt-controller: identifies the node as an interrupt controller
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Driscv,aplic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,aplic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Advanced Platform Level Interrupt Controller (APLIC)
10 - Anup Patel <[email protected]>
13 The RISC-V advanced interrupt architecture (AIA) defines an advanced
14 platform level interrupt controller (APLIC) for handling wired interrupts
15 in a RISC-V platform. The RISC-V AIA specification can be found at
16 https://github.com/riscv/riscv-aia.
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Dopen-pic.txt4 representation of an Open PIC compliant interrupt controller. This binding is
5 based on the binding defined for Open PIC in [1] and is a superset of that
13 - compatible: Specifies the compatibility list for the PIC. The type
14 shall be <string> and the value shall include "open-pic".
16 - reg: Specifies the base physical address(s) and size(s) of this
17 PIC's addressable register space. The type shall be <prop-encoded-array>.
19 - interrupt-controller: The presence of this property identifies the node
22 - #interrupt-cells: Specifies the number of cells needed to encode an
25 - #address-cells: Specifies the number of cells needed to encode an
27 'interrupt-map' nodes do not have to specify a parent unit address.
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/linux-6.14.4/arch/mips/include/asm/
Dmmu_context.h4 * This file is subject to the terms and conditions of the GNU General Public
26 #include <asm-generic/mm_hooks.h>
39 /* Note: This is also implemented with uasm in arch/mips/kvm/entry.c */
62 * to the current pgd for each processor. Also, the proc. id is stuffed
78 * The ginvt instruction will invalidate wired entries when its type field
80 * allow the kernel to create wired entries with the MMID of current->active_mm
81 * then those wired entries could be invalidated when we later use ginvt to
84 * In order to prevent ginvt from trashing wired entries, we reserve one MMID
85 * for use by the kernel when creating wired entries. This MMID will never be
98 return ~(u64)(asid_mask | (asid_mask - 1)); in asid_version_mask()
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Dregdef.h2 * This file is subject to the terms and conditions of the GNU General Public
8 * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc.
10 * written by Ralf Baechle <ralf@linux-mips.org>
22 #define GPR_ZERO 0 /* wired zero */
65 #define GPR_ZERO 0 /* wired zero */
67 #define GPR_V0 2 /* return value - caller saved */
98 #define GPR_GP 28 /* global pointer - caller saved for PIC */
112 #define zero $0 /* wired zero */
113 #define AT $1 /* assembler temp - uppercase because of ".set at" */
155 #define zero $0 /* wired zero */
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/linux-6.14.4/Documentation/devicetree/bindings/iio/resolver/
Dadi,ad2s1210.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AD2S1210 Resolver-to-Digital Converter
10 - Michael Hennerich <[email protected]>
13 The AD2S1210 is a complete 10-bit to 16-bit resolution tracking
14 resolver-to-digital converter, integrating an on-board programmable
22 The mode of operation of the communication channel (parallel or serial) is
23 selected by the A0 and A1 input pins. In normal mode, data is latched by
25 data is read or written using a register access scheme (address byte with
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/linux-6.14.4/arch/sh/mm/
Dtlb-urb.c2 * arch/sh/mm/tlb-urb.c
4 * TLB entry wiring helpers for URB-equipped parts.
8 * This file is subject to the terms and conditions of the GNU General Public
34 BUG_ON(!--urb); in tlb_wire_entry()
39 * Insert this entry into the highest non-wired TLB slot (via in tlb_wire_entry()
62 * Unwire the last wired TLB entry.
64 * It should also be noted that it is not possible to wire and unwire
82 * have been wired. in tlb_unwire_entry()
/linux-6.14.4/Documentation/devicetree/bindings/iommu/
Driscv,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V IOMMU Architecture Implementation
10 - Tomasz Jeznach <[email protected]>
13 The RISC-V IOMMU provides memory address translation and isolation for
14 input and output devices, supporting per-device translation context,
17 It supports identical translation table format to the RISC-V address
19 Hardware uses in-memory command and fault reporting queues with wired
22 Visit https://github.com/riscv-non-isa/riscv-iommu for more details.
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/linux-6.14.4/arch/mips/sgi-ip30/
Dip30-common.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Power Switch is wired via BaseIO BRIDGE slot #6.
9 * ACFail is wired via BaseIO BRIDGE slot #7.
/linux-6.14.4/Documentation/devicetree/bindings/spi/
Dspi-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a SPI bus.
11 be common properties like spi-max-frequency, spi-cpha, etc. or they could be
13 need to be defined in the peripheral node because they are per-peripheral and
19 - Mark Brown <[email protected]>
27 - minimum: 0
32 spi-cs-high:
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/linux-6.14.4/arch/arm/boot/dts/allwinner/
Dsun8i-v3s-anbernic-rg-nano.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include "sun8i-v3s.dtsi"
6 #include "sunxi-common-regulators.dtsi"
10 compatible = "anbernic,rg-nano", "allwinner,sun8i-v3s";
19 compatible = "pwm-backlight";
20 brightness-levels = <0 1 2 3 8 14 21 32 46 60 80 100>;
21 default-brightness-level = <11>;
22 power-supply = <&reg_vcc5v0>;
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/linux-6.14.4/arch/mips/kvm/
Dvz.c2 * This file is subject to the terms and conditions of the GNU General Public
62 * write_gc0_ebase_64() is no longer UNDEFINED since R6. in kvm_vz_write_gc0_ebase()
115 if (kvm_mips_guest_has_msa(&vcpu->arch)) in kvm_vz_config5_guest_wrmask()
119 * Permit guest FPU mode changes if FPU is enabled and the relevant in kvm_vz_config5_guest_wrmask()
122 if (kvm_mips_guest_has_fpu(&vcpu->arch)) { in kvm_vz_config5_guest_wrmask()
140 * Config1: M, [MMUSize-1, C2, MD, PC, WR, CA], FP
157 /* Permit FPU to be present if FPU is supported */ in kvm_vz_config1_user_wrmask()
158 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) in kvm_vz_config1_user_wrmask()
174 /* Permit MSA to be present if MSA is supported */ in kvm_vz_config3_user_wrmask()
175 if (kvm_mips_guest_can_have_msa(&vcpu->arch)) in kvm_vz_config3_user_wrmask()
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/linux-6.14.4/drivers/input/joystick/
Dxpad.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2002 Marko Friedemann <mfr@bmx-chemnitz.de>
15 * This driver is based on:
16 * - information from http://euc.jp/periphs/xbox-controller.ja.html
17 * - the iForce driver drivers/char/joystick/iforce.c
18 * - the skeleton-driver drivers/usb/usb-skeleton.c
19 * - Xbox 360 information http://www.free60.org/wiki/Gamepad
20 * - Xbox One information https://github.com/quantus/xbox-one-controller-protocol
23 * - ITO Takayuki for providing essential xpad information on his website
24 * - Vojtech Pavlik - iforce driver / input subsystem
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/linux-6.14.4/Documentation/hwmon/
Dvia686a.rst10 Addresses scanned: ISA in PCI-space encoded address
12 Datasheet: On request through web form (http://www.via.com.tw/en/resources/download-center/)
15 - Kyösti Mälkki <[email protected]>,
16 - Mark D. Studebaker <[email protected]>
17 - Bob Dougherty <[email protected]>
18 - (Some conversion-factor data were contributed by
19 - Jonathan Teh Soon Yew <[email protected]>
20 - and Alex van Kaam <[email protected]>.)
23 -----------------
31 base address is not set.
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Dsmsc47m192.rst10 Addresses scanned: I2C 0x2c - 0x2d
12 Datasheet: The datasheet for LPC47M192 is publicly available from
23 - Hartmut Rick <[email protected]>
25 - Special thanks to Jean Delvare for careful checking
30 -----------
33 of the SMSC LPC47M192 and compatible Super-I/O chips.
42 Voltages and temperatures are measured by an 8-bit ADC, the resolution
43 of the temperatures is 1 bit per degree C.
46 each voltage channel is 0V ... 255/192*(nominal voltage), the resolution
47 is 1 bit per (nominal voltage)/192.
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/linux-6.14.4/Documentation/devicetree/bindings/display/bridge/
Dsil,sii9022.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Boris Brezillon <[email protected]>
15 - items:
16 - enum:
17 - sil,sii9022-cpi # CEC Programming Interface
18 - sil,sii9022-tpi # Transmitter Programming Interface
19 - const: sil,sii9022
20 - const: sil,sii9022
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/linux-6.14.4/arch/arm/boot/dts/st/
Dste-href-tvk1281618-r2.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/input/input.h>
11 compatible = "gpio-keys";
12 #address-cells = <1>;
13 #size-cells = <0>;
14 vdd-supply = <&ab8500_ldo_aux1_reg>;
15 pinctrl-names = "default";
16 pinctrl-0 = <&prox_tvk_mode>, <&hall_tvk_mode>;
37 interrupt-parent = <&gpio6>;
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/linux-6.14.4/Documentation/devicetree/bindings/net/dsa/
Dmediatek,mt7530.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <[email protected]>
11 - Landen Chao <[email protected]>
12 - DENG Qingfang <[email protected]>
13 - Sean Wang <[email protected]>
14 - Daniel Golle <[email protected]>
17 There are three versions of MT7530, standalone, in a multi-chip module and
18 built-into a SoC.
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