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/linux-6.14.4/drivers/iommu/
Dmsm_iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
13 #include <linux/io-pgtable.h>
18 #include <linux/iommu.h>
25 #include "msm_iommu_hw-8xxx.h"
54 static int __enable_clocks(struct msm_iommu_dev *iommu) in __enable_clocks() argument
58 ret = clk_enable(iommu->pclk); in __enable_clocks()
62 if (iommu->clk) { in __enable_clocks()
63 ret = clk_enable(iommu->clk); in __enable_clocks()
65 clk_disable(iommu->pclk); in __enable_clocks()
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Dmtk_iommu_v1.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * IOMMU API for MTK architected m4u v1 implementations
5 * Copyright (c) 2015-2016 MediaTek Inc.
8 * Based on driver/iommu/mtk_iommu.c
14 #include <linux/dma-mapping.h>
18 #include <linux/iommu.h>
30 #include <asm/dma-iommu.h>
31 #include <dt-bindings/memory/mtk-memory-port.h>
32 #include <dt-bindings/memory/mt2701-larb-port.h>
77 #define MT2701_M4U_TF_LARB(TF) (6 - (((TF) >> 13) & 0x7))
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Dsprd-iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Unisoc IOMMU driver
11 #include <linux/dma-mapping.h>
13 #include <linux/iommu.h>
52 * struct sprd_iommu_device - high-level sprd IOMMU device representation,
55 * @ver: sprd IOMMU IP version
56 * @prot_page_va: protect page base virtual address
57 * @prot_page_pa: protect page base physical address, data would be
59 * @base: mapped base address for accessing registers
61 * @iommu: IOMMU core representation
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Dsun50i-iommu.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 // Copyright (C) 2016-2018, Allwinner Technology CO., LTD.
3 // Copyright (C) 2019-2020, Cerno
9 #include <linux/dma-direction.h>
10 #include <linux/dma-mapping.h>
14 #include <linux/iommu.h>
29 #include "iommu-pages.h"
101 struct iommu_device iommu; member
103 /* Lock to modify the IOMMU registers */
107 void __iomem *base; member
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Dmtk_iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015-2016 MediaTek Inc.
6 #include <linux/arm-smccc.h>
15 #include <linux/iommu.h>
17 #include <linux/io-pgtable.h>
36 #include <dt-bindings/memory/mtk-memory-port.h>
138 #define STD_AXI_MODE BIT(12) /* For non MM iommu */
139 /* 2 bits: iommu type */
143 /* PM and clock always on. e.g. infra iommu */
152 ((((pdata)->flags) & (mask)) == (_x))
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Drockchip-iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * IOMMU API for Rockchip
5 * Module Authors: Simon Xue <xxm@rock-chips.com>
13 #include <linux/dma-mapping.h>
17 #include <linux/iommu.h>
30 #include "iommu-pages.h"
39 #define RK_MMU_INT_CLEAR 0x18 /* Acknowledge and re-arm irq */
63 #define RK_MMU_CMD_DISABLE_STALL 3 /* Stop stall re-enables paging */
95 /* list of clocks required by IOMMU */
116 struct iommu_device iommu; member
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Domap-iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap iommu: tlb and pagetable primitives
5 * Copyright (C) 2008-2010 Nokia Corporation
6 * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
12 #include <linux/dma-mapping.h>
18 #include <linux/iommu.h>
19 #include <linux/omap-iommu.h>
30 #include <linux/platform_data/iommu-omap.h>
32 #include "omap-iopgtable.h"
33 #include "omap-iommu.h"
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/linux-6.14.4/arch/sparc/kernel/
Diommu.c1 // SPDX-License-Identifier: GPL-2.0
2 /* iommu.c: Generic sparc64 IOMMU support.
13 #include <linux/dma-map-ops.h>
15 #include <linux/iommu-helper.h>
17 #include <asm/iommu-common.h>
23 #include <asm/iommu.h>
29 ((STC)->strbuf_ctxmatch_base + ((CTX) << 3))
31 (*((STC)->strbuf_flushflag) = 0UL)
33 (*((STC)->strbuf_flushflag) != 0UL)
49 /* Must be invoked under the IOMMU lock. */
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Dpci_psycho.c1 // SPDX-License-Identifier: GPL-2.0
20 #include <asm/iommu.h>
61 /* Helper function of IOMMU error checking, which checks out
62 * the state of the streaming buffers. The IOMMU lock is
90 * interrogate the IOMMU state to see if it is the cause.
99 #define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
100 #define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
101 #define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
102 #define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
103 #define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
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Dpsycho_common.c1 // SPDX-License-Identifier: GPL-2.0
39 struct strbuf *strbuf = &pbm->stc; in psycho_check_stc_error()
43 if (!strbuf->strbuf_control) in psycho_check_stc_error()
46 err_base = strbuf->strbuf_err_stat; in psycho_check_stc_error()
47 tag_base = strbuf->strbuf_tag_diag; in psycho_check_stc_error()
48 line_base = strbuf->strbuf_line_diag; in psycho_check_stc_error()
55 * before re-enabling the streaming buffer. If any dirty data in psycho_check_stc_error()
60 control = upa_readq(strbuf->strbuf_control); in psycho_check_stc_error()
61 upa_writeq(control | PSYCHO_STRBUF_CTRL_DENAB, strbuf->strbuf_control); in psycho_check_stc_error()
77 upa_writeq(control, strbuf->strbuf_control); in psycho_check_stc_error()
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Dpci_sun4v.c1 // SPDX-License-Identifier: GPL-2.0
20 #include <linux/dma-map-ops.h>
21 #include <asm/iommu-common.h>
23 #include <asm/iommu.h>
58 unsigned long prot; /* IOMMU page protections */
72 p->dev = dev; in iommu_batch_start()
73 p->prot = prot; in iommu_batch_start()
74 p->entry = entry; in iommu_batch_start()
75 p->npages = 0; in iommu_batch_start()
78 static inline bool iommu_use_atu(struct iommu *iommu, u64 mask) in iommu_use_atu() argument
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/linux-6.14.4/arch/powerpc/platforms/cell/
Diommu.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * IOMMU implementation for Cell Broadband Processor Architecture
5 * (C) Copyright IBM Corporation 2006-2008
24 #include <asm/iommu.h>
26 #include <asm/pci-bridge.h>
29 #include <asm/cell-regs.h>
34 /* Define CELL_IOMMU_REAL_UNMAP to actually unmap non-used pages
43 * once spider-net has been fixed to pass the correct direction
86 #define IOSTE_PT_Base_RPN_Mask 0x3ffffffffffff000ul /* base RPN of IOPT */
89 #define IOSTE_PS_4K 0x0000000000000001ul /* - 4kB */
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/linux-6.14.4/Documentation/devicetree/bindings/pci/
Dpci-iommu.txt2 relationship between PCI(e) devices and IOMMU(s).
17 Requester ID. While a given PCI device can only master through one IOMMU, a
18 root complex may split masters across a set of IOMMUs (e.g. with one IOMMU per
22 and a mechanism is required to map from a PCI device to its IOMMU and sideband
25 For generic IOMMU bindings, see
26 Documentation/devicetree/bindings/iommu/iommu.txt.
33 -------------------
35 - iommu-map: Maps a Requester ID to an IOMMU and associated IOMMU specifier
39 (rid-base,iommu,iommu-base,length).
41 Any RID r in the interval [rid-base, rid-base + length) is associated with
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/linux-6.14.4/Documentation/ABI/testing/
Ddebugfs-intel-iommu1 What: /sys/kernel/debug/iommu/intel/iommu_regset
5 This file dumps all the register contents for each IOMMU device.
11 $ sudo cat /sys/kernel/debug/iommu/intel/iommu_regset
13 IOMMU: dmar0 Register Base Address: 26be37000
24 IOMMU: dmar1 Register Base Address: fed90000
35 IOMMU: dmar2 Register Base Address: fed91000
46 What: /sys/kernel/debug/iommu/intel/ir_translation_struct
57 $ sudo cat /sys/kernel/debug/iommu/intel/ir_translation_struct
59 Remapped Interrupt supported on IOMMU: dmar0
66 Remapped Interrupt supported on IOMMU: dmar1
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/linux-6.14.4/drivers/gpu/drm/msm/
Dmsm_iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/adreno-smmu-priv.h>
8 #include <linux/io-pgtable.h>
13 struct msm_mmu base; member
18 #define to_msm_iommu(x) container_of(x, struct msm_iommu, base)
21 struct msm_mmu base; member
32 return container_of(mmu, struct msm_iommu_pagetable, base); in to_pagetable()
35 /* based on iommu_pgsize() in iommu.c: */
46 pgsizes = pagetable->pgsize_bitmap & GENMASK(__fls(size), 0); in calc_pgsize()
62 pgsizes = pagetable->pgsize_bitmap & ~GENMASK(pgsize_idx, 0); in calc_pgsize()
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/linux-6.14.4/Documentation/devicetree/bindings/misc/
Dfsl,qoriq-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/misc/fsl,qoriq-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <[email protected]>
13 The Freescale Management Complex (fsl-mc) is a hardware resource
15 network-oriented packet processing applications. After the fsl-mc
22 For an overview of the DPAA2 architecture and fsl-mc bus see:
26 same hardware "isolation context" and a 10-bit value called an ICID
31 between ICIDs and IOMMUs, so an iommu-map property is used to define
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/linux-6.14.4/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/
Dgk20a.c30 * 1) If an IOMMU unit has been probed, the IOMMU API is used to make memory
32 * 2) If no IOMMU unit is probed, the DMA API is used to allocate physically
35 * In both cases CPU read and writes are performed by creating a write-combined
52 struct nvkm_instobj base; member
59 #define gk20a_instobj(p) container_of((p), struct gk20a_instobj, base.memory)
65 struct gk20a_instobj base; member
71 container_of(gk20a_instobj(p), struct gk20a_instobj_dma, base)
74 * Used for objects flattened using the IOMMU API
77 struct gk20a_instobj base; member
86 /* array of base.mem->size pages (+ dma_addr_ts) */
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/linux-6.14.4/drivers/iommu/intel/
Ddebugfs.c1 // SPDX-License-Identifier: GPL-2.0
17 #include "iommu.h"
116 struct intel_iommu *iommu; in iommu_regset_show() local
122 for_each_active_iommu(iommu, drhd) { in iommu_regset_show()
123 if (!drhd->reg_base_addr) { in iommu_regset_show()
124 seq_puts(m, "IOMMU: Invalid base address\n"); in iommu_regset_show()
125 ret = -EINVAL; in iommu_regset_show()
129 seq_printf(m, "IOMMU: %s Register Base Address: %llx\n", in iommu_regset_show()
130 iommu->name, drhd->reg_base_addr); in iommu_regset_show()
133 * Publish the contents of the 64-bit hardware registers in iommu_regset_show()
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Dirq_remapping.c1 // SPDX-License-Identifier: GPL-2.0
3 #define pr_fmt(fmt) "DMAR-IR: " fmt
21 #include <asm/pci-direct.h>
24 #include "iommu.h"
26 #include "../iommu-pages.h"
29 struct intel_iommu *iommu; member
36 struct intel_iommu *iommu; member
43 struct intel_iommu *iommu; member
68 * ->dmar_global_lock
69 * ->irq_2_ir_lock
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/linux-6.14.4/drivers/iommu/riscv/
Diommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * IOMMU API for RISC-V IOMMU implementations.
5 * Copyright © 2022-2024 Rivos Inc.
6 * Copyright © 2023 FORTH-ICS/CARV
13 #define pr_fmt(fmt) "riscv-iommu: " fmt
18 #include <linux/iommu.h>
23 #include "../iommu-pages.h"
24 #include "iommu-bits.h"
25 #include "iommu.h"
37 /* RISC-V IOMMU PPN <> PHYS address conversions, PHYS <=> PPN[53:10] */
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Diommu.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2022-2024 Rivos Inc.
4 * Copyright © 2023 FORTH-ICS/CARV
14 #include <linux/iommu.h>
18 #include "iommu-bits.h"
26 unsigned int mask; /* index mask, queue length - 1 */
28 struct riscv_iommu_device *iommu; /* iommu device handling the queue when active */ member
29 void *base; /* ring buffer kernel pointer */ member
31 u16 qbr; /* base register offset, head and tail reference */
37 /* iommu core interface */
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/linux-6.14.4/Documentation/arch/x86/
Diommu.rst2 x86 IOMMU Support
7 - Intel: http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/vt-dire…
8 - AMD: https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/specifications/48882_3_…
13 -----------
16 device scope relationships between devices and which IOMMU controls
21 - DMAR - Intel DMA Remapping table
22 - DRHD - Intel DMA Remapping Hardware Unit Definition
23 - RMRR - Intel Reserved Memory Region Reporting Structure
24 - IVRS - AMD I/O Virtualization Reporting Structure
25 - IVDB - AMD I/O Virtualization Definition Block
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/linux-6.14.4/arch/sparc/include/asm/
Diommu_64.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* iommu.h: Definitions for the sun5 IOMMU.
20 #include <asm/iommu-common.h>
32 void *table; /* IOTSB table base virtual addr*/
35 u64 dvma_base; /* ranges[3].base */
42 u64 base; member
50 u64 base; member
55 struct iommu { struct
86 volatile unsigned long __flushflag_buf[(64+(64-1)) / sizeof(long)];
89 int iommu_table_init(struct iommu *iommu, int tsbsize, argument
/linux-6.14.4/drivers/iommu/arm/arm-smmu/
Dqcom_iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * IOMMU API for QCOM secure IOMMUs. Somewhat based on arm-smmu.c
13 #include <linux/dma-mapping.h>
17 #include <linux/io-64-nonatomic-hi-lo.h>
18 #include <linux/io-pgtable.h>
19 #include <linux/iommu.h>
33 #include "arm-smmu.h"
47 /* IOMMU core code handle */
48 struct iommu_device iommu; member
59 void __iomem *base; member
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/linux-6.14.4/arch/sparc/mm/
Diommu.c1 // SPDX-License-Identifier: GPL-2.0
3 * iommu.c: IOMMU specific routines for memory management.
15 #include <linux/dma-map-ops.h>
26 #include <asm/iommu.h>
60 struct iommu_struct *iommu; in sbus_iommu_init() local
64 unsigned long base; in sbus_iommu_init() local
67 iommu = kmalloc(sizeof(struct iommu_struct), GFP_KERNEL); in sbus_iommu_init()
68 if (!iommu) { in sbus_iommu_init()
69 prom_printf("Unable to allocate iommu structure\n"); in sbus_iommu_init()
73 iommu->regs = of_ioremap(&op->resource[0], 0, PAGE_SIZE * 3, in sbus_iommu_init()
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