Searched +full:imx8ulp +full:- +full:cgc1 (Results 1 – 4 of 4) sorted by relevance
| /linux-6.14.4/arch/arm64/boot/dts/freescale/ |
| D | imx8ulp.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8ulp-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/power/imx8ulp-power.h>
10 #include <dt-bindings/thermal/thermal.h>
12 #include "imx8ulp-pinfunc.h"
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
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| D | imx8ulp-evk.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "imx8ulp.dtsi"
12 compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";
14 bt_sco_codec: bt-sco-codec {
15 #sound-dai-cells = <1>;
16 compatible = "linux,bt-sco";
20 stdout-path = &lpuart5;
28 reserved-memory {
29 #address-cells = <2>;
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| /linux-6.14.4/Documentation/devicetree/bindings/clock/ |
| D | imx8ulp-cgc-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8ulp-cgc-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacky Bai <[email protected]>
20 - fsl,imx8ulp-cgc1
21 - fsl,imx8ulp-cgc2
26 '#clock-cells':
30 - compatible
31 - reg
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| /linux-6.14.4/drivers/clk/imx/ |
| D | clk-imx8ulp.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx8ulp-clock.h>
12 #include <linux/reset-controller.h>
85 u32 offset = pcc_reset->resets[id]; in imx8ulp_pcc_assert()
89 spin_lock_irqsave(pcc_reset->lock, flags); in imx8ulp_pcc_assert()
91 val = readl(pcc_reset->base + offset); in imx8ulp_pcc_assert()
93 writel(val, pcc_reset->base + offset); in imx8ulp_pcc_assert()
95 spin_unlock_irqrestore(pcc_reset->lock, flags); in imx8ulp_pcc_assert()
103 u32 offset = pcc_reset->resets[id]; in imx8ulp_pcc_deassert()
107 spin_lock_irqsave(pcc_reset->lock, flags); in imx8ulp_pcc_deassert()
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