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/linux-6.14.4/Documentation/devicetree/bindings/phy/
Dfsl,imx8qm-hsio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8qm-hsio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8QM SoC series High Speed IO(HSIO) SERDES PHY
10 - Richard Zhu <[email protected]>
15 - fsl,imx8qm-hsio
16 - fsl,imx8qxp-hsio
19 - description: Base address and length of the PHY block
20 - description: HSIO control and status registers(CSR) of the PHY
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/linux-6.14.4/drivers/phy/freescale/
Dphy-fsl-imx8qm-hsio.c1 // SPDX-License-Identifier: GPL-2.0+
19 #include <dt-bindings/phy/phy.h>
20 #include <dt-bindings/phy/phy-imx8-pcie.h>
29 /* i.MX8Q HSIO registers */
120 struct imx_hsio_priv *priv = lane->priv; in imx_hsio_init()
121 struct device *dev = priv->dev; in imx_hsio_init()
124 switch (lane->phy_type) { in imx_hsio_init()
126 lane->phy_mode = PHY_MODE_PCIE; in imx_hsio_init()
127 if (lane->ctrl_index == 0) { /* PCIEA */ in imx_hsio_init()
128 lane->ctrl_off = 0; in imx_hsio_init()
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/linux-6.14.4/arch/arm64/boot/dts/freescale/
Dimx8dxl-evk.dts1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
12 compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl";
24 stdout-path = &lpuart0;
27 imx8dxl-cm4 {
28 compatible = "fsl,imx8qxp-cm4";
30 mbox-names = "tx", "rx", "rxdb";
32 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
34 power-domains = <&pd IMX_SC_R_M4_0_PID0>, <&pd IMX_SC_R_M4_0_MU_1A>;
35 fsl,resource-id = <IMX_SC_R_M4_0_PID0>;
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Dimx8qxp-mek.dts1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
9 #include <dt-bindings/usb/pd.h>
13 compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
15 bt_sco_codec: audio-codec-bt {
16 compatible = "linux,bt-sco";
17 #sound-dai-cells = <1>;
21 stdout-path = &lpuart0;
24 imx8x_cm4: imx8x-cm4 {
25 compatible = "fsl,imx8qxp-cm4";
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Dimx8qm-mek.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 /dts-v1/;
9 #include <dt-bindings/usb/pd.h>
14 compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
17 stdout-path = &lpuart0;
21 /delete-node/ cpu-map;
22 /delete-node/ cpu@100;
23 /delete-node/ cpu@101;
26 thermal-zones {
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/linux-6.14.4/include/soc/mscc/
Docelot.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
23 * - In one of PGID[0-63]: for the destination masks. There are 2 paths by
25 * - The {DMAC, VID} is present in the MAC table. In that case, the
28 * - The {DMAC, VID} is not present in the MAC table (it is unknown). The
34 * ocelot->num_phys_ports - 1, or a multicast set: the PGIDs from
35 * ocelot->num_phys_ports to 63. By convention, a unicast PGID corresponds to
40 * - In one of PGID[64-79]: for the aggregation mask. The switch classifier
41 * dissects each frame and generates a 4-bit Link Aggregation Code which is
48 * - In one of PGID[80-90]: for the source mask. The third time, the PGID table
60 * PGID_MC: the flooding destinations for non-IP multicast traffic.
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/linux-6.14.4/drivers/net/dsa/ocelot/
Dfelix.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright 2019-2021 NXP
5 * register-compatible with Ocelot and that perform I/O to their host CPU
41 return ERR_PTR(-EOPNOTSUPP); in felix_classify_db()
48 struct ocelot *ocelot = ds->priv; in felix_cpu_port_for_conduit()
53 mutex_lock(&ocelot->fwd_domain_lock); in felix_cpu_port_for_conduit()
55 mutex_unlock(&ocelot->fwd_domain_lock); in felix_cpu_port_for_conduit()
60 cpu_dp = conduit->dsa_ptr; in felix_cpu_port_for_conduit()
61 return cpu_dp->index; in felix_cpu_port_for_conduit()
65 * felix_update_tag_8021q_rx_rule - Update VCAP ES0 tag_8021q rule after
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