| /linux-6.14.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
| D | gm200.c | 37 nvkm_warn(&gr->base.engine.subdev, "firmware unavailable\n"); in gm200_gr_nofw()
38 return -ENODEV; in gm200_gr_nofw()
42 * PGRAPH engine/subdev functions
48 struct flcn_bl_dmem_desc_v1 hdr; in gm200_gr_acr_bld_patch() local
49 nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr)); in gm200_gr_acr_bld_patch()
50 hdr.code_dma_base = hdr.code_dma_base + adjust; in gm200_gr_acr_bld_patch()
51 hdr.data_dma_base = hdr.data_dma_base + adjust; in gm200_gr_acr_bld_patch()
52 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr)); in gm200_gr_acr_bld_patch()
53 flcn_bl_dmem_desc_v1_dump(&acr->subdev, &hdr); in gm200_gr_acr_bld_patch()
60 const u64 base = lsfw->offset.img + lsfw->app_start_offset; in gm200_gr_acr_bld_write()
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| D | gm20b.c | 36 struct flcn_bl_dmem_desc hdr; in gm20b_gr_acr_bld_patch() local
39 nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr)); in gm20b_gr_acr_bld_patch()
40 addr = ((u64)hdr.code_dma_base1 << 40 | hdr.code_dma_base << 8); in gm20b_gr_acr_bld_patch()
41 hdr.code_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
42 hdr.code_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
43 addr = ((u64)hdr.data_dma_base1 << 40 | hdr.data_dma_base << 8); in gm20b_gr_acr_bld_patch()
44 hdr.data_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
45 hdr.data_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
46 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr)); in gm20b_gr_acr_bld_patch()
48 flcn_bl_dmem_desc_dump(&acr->subdev, &hdr); in gm20b_gr_acr_bld_patch()
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| D | gm107.c | 284 * PGRAPH engine/subdev functions
290 nvkm_wr32(gr->base.engine.subdev.device, 0x400054, 0x2c350f63); in gm107_gr_init_400054()
296 struct nvkm_device *device = gr->base.engine.subdev.device; in gm107_gr_init_shader_exceptions()
304 struct nvkm_device *device = gr->base.engine.subdev.device; in gm107_gr_init_504430()
311 struct nvkm_subdev *subdev = &gr->base.engine.subdev; in gm107_gr_init_bios_2()
312 struct nvkm_device *device = subdev->device; in gm107_gr_init_bios_2()
313 struct nvkm_bios *bios = device->bios; in gm107_gr_init_bios_2()
320 u8 hdr = nvbios_rd08(bios, data + 0x01); in gm107_gr_init_bios_2() local
321 if (ver == 0x20 && hdr >= 8) { in gm107_gr_init_bios_2()
346 struct nvkm_device *device = gr->base.engine.subdev.device; in gm107_gr_init_bios()
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| /linux-6.14.4/drivers/gpu/drm/nouveau/nvkm/engine/sec2/ |
| D | gp102.c | 35 nvkm_warn(&sec2->engine.subdev, "firmware unavailable\n"); in gp102_sec2_nofw()
40 gp102_sec2_acr_bootstrap_falcon_callback(void *priv, struct nvfw_falcon_msg *hdr) in gp102_sec2_acr_bootstrap_falcon_callback() argument
43 container_of(hdr, typeof(*msg), msg.hdr); in gp102_sec2_acr_bootstrap_falcon_callback()
45 const char *name = nvkm_acr_lsf_id(msg->falcon_id); in gp102_sec2_acr_bootstrap_falcon_callback()
47 if (msg->error_code) { in gp102_sec2_acr_bootstrap_falcon_callback()
50 msg->falcon_id, name, msg->error_code); in gp102_sec2_acr_bootstrap_falcon_callback()
51 return -EINVAL; in gp102_sec2_acr_bootstrap_falcon_callback()
64 .cmd.hdr.unit_id = sec2->func->unit_acr, in gp102_sec2_acr_bootstrap_falcon()
65 .cmd.hdr.size = sizeof(cmd), in gp102_sec2_acr_bootstrap_falcon()
71 return nvkm_falcon_cmdq_send(sec2->cmdq, &cmd.cmd.hdr, in gp102_sec2_acr_bootstrap_falcon()
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| D | ga102.c | 36 ret = nvkm_falcon_msgq_recv_initmsg(sec2->msgq, &msg, sizeof(msg)); in ga102_sec2_initmsg()
40 if (msg.hdr.unit_id != NV_SEC2_UNIT_INIT || in ga102_sec2_initmsg()
42 return -EINVAL; in ga102_sec2_initmsg()
46 nvkm_falcon_msgq_init(sec2->msgq, msg.queue_info[i].index, in ga102_sec2_initmsg()
50 nvkm_falcon_cmdq_init(sec2->cmdq, msg.queue_info[i].index, in ga102_sec2_initmsg()
62 struct nvkm_device *device = sec2->engine.subdev.device; in ga102_sec2_intr_vector()
63 struct nvkm_falcon *falcon = &sec2->falcon; in ga102_sec2_intr_vector()
71 return &device->vfn->intr; in ga102_sec2_intr_vector()
75 ga102_sec2_acr_bootstrap_falcon_callback(void *priv, struct nvfw_falcon_msg *hdr) in ga102_sec2_acr_bootstrap_falcon_callback() argument
78 container_of(hdr, typeof(*msg), msg.hdr); in ga102_sec2_acr_bootstrap_falcon_callback()
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| D | base.c | 31 nvkm_sec2_finimsg(void *priv, struct nvfw_falcon_msg *hdr) in nvkm_sec2_finimsg() argument
35 atomic_set(&sec2->running, 0); in nvkm_sec2_finimsg()
40 nvkm_sec2_fini(struct nvkm_engine *engine, bool suspend) in nvkm_sec2_fini() argument
42 struct nvkm_sec2 *sec2 = nvkm_sec2(engine); in nvkm_sec2_fini()
43 struct nvkm_subdev *subdev = &sec2->engine.subdev; in nvkm_sec2_fini()
44 struct nvkm_falcon *falcon = &sec2->falcon; in nvkm_sec2_fini()
45 struct nvkm_falcon_cmdq *cmdq = sec2->cmdq; in nvkm_sec2_fini()
47 .unit_id = sec2->func->unit_unload, in nvkm_sec2_fini()
52 if (!subdev->use.enabled) in nvkm_sec2_fini()
55 if (atomic_read(&sec2->initmsg) == 1) { in nvkm_sec2_fini()
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| /linux-6.14.4/drivers/gpu/drm/i915/gt/uc/ |
| D | intel_guc_capture.c | 1 // SPDX-License-Identifier: MIT
3 * Copyright © 2021-2022 Intel Corporation
27 * NOTE: For engine-registers, GuC only needs the register offsets
28 * from the engine-mmio-base
104 /* XE_LP Render / Compute Per-Class */
110 /* GEN8+ Render / Compute Per-Engine-Instance */
115 /* GEN8+ Media Decode/Encode Per-Engine-Instance */
120 /* XE_LP Video Enhancement Per-Class */
125 /* GEN8+ Video Enhancement Per-Engine-Instance */
130 /* GEN8+ Blitter Per-Engine-Instance */
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| /linux-6.14.4/drivers/gpu/drm/i915/gt/ |
| D | intel_engine_cs.c | 1 // SPDX-License-Identifier: MIT
40 * on HSW) - so the final size, including the extra state required for the
260 * intel_engine_context_size() - return the size of the context for an engine
262 * @class: engine class
264 * Each engine class may require a different amount of space for a context
267 * Return: size (in bytes) of an engine class specific context image
275 struct intel_uncore *uncore = gt->uncore; in intel_engine_context_size()
284 switch (GRAPHICS_VER(gt->i915)) { in intel_engine_context_size()
286 MISSING_CASE(GRAPHICS_VER(gt->i915)); in intel_engine_context_size()
296 if (IS_HASWELL(gt->i915)) in intel_engine_context_size()
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| D | intel_migrate.c | 1 // SPDX-License-Identifier: MIT
23 static bool engine_supports_migration(struct intel_engine_cs *engine) in engine_supports_migration() argument
25 if (!engine) in engine_supports_migration()
33 GEM_BUG_ON(engine->class != COPY_ENGINE_CLASS); in engine_supports_migration()
48 vm->insert_page(vm, 0, d->offset, in xehp_toggle_pdes()
49 i915_gem_get_pat_index(vm->i915, I915_CACHE_NONE), in xehp_toggle_pdes()
51 GEM_BUG_ON(!pt->is_compact); in xehp_toggle_pdes()
52 d->offset += SZ_2M; in xehp_toggle_pdes()
68 vm->insert_page(vm, px_dma(pt), d->offset, in xehp_insert_pte()
69 i915_gem_get_pat_index(vm->i915, I915_CACHE_NONE), in xehp_insert_pte()
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| /linux-6.14.4/drivers/gpu/drm/xe/ |
| D | xe_guc_capture.c | 1 // SPDX-License-Identifier: MIT
3 * Copyright © 2021-2024 Intel Corporation
45 * Book-keeping structure used to track read and write pointers
46 * as we extract error capture data from the GuC-log-buffer's
47 * error-capture region as a stream of dwords.
57 * struct __guc_capture_parsed_output - extracted error capture node
59 * A single unit of extracted error-capture output data grouped together
60 * at an engine-instance level. We keep these nodes in a linked list.
65 * A single set of 3 capture lists: a global-list
66 * an engine-class-list and an engine-instance list.
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| /linux-6.14.4/drivers/crypto/ |
| D | sahara.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 * Author: Javier Martin <javier.martin@vista-silicon.com>
11 * Based on omap-aes.c and tegra-aes.c
18 #include <crypto/engine.h>
23 #include <linux/dma-mapping.h>
125 u32 hdr; member
140 /* AES-specific context */
153 * struct sahara_sha_reqctx - private data per request
155 * @rembuf: used to prepare one block_size-aligned request
156 * @context: hw-specific context for request. Digest is extracted from this
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| /linux-6.14.4/Documentation/devicetree/bindings/display/mediatek/ |
| D | mediatek,ethdr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <[email protected]>
11 - Philipp Zabel <[email protected]>
14 ETHDR (ET High Dynamic Range) is a MediaTek internal HDR engine and is
15 designed for HDR video and graphics conversion in the external display path.
16 It handles multiple HDR input types and performs tone mapping, color
18 output the required HDR or SDR signal to the subsequent display path.
19 This engine is composed of two video frontends, two graphic frontends,
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| /linux-6.14.4/drivers/crypto/marvell/octeontx2/ |
| D | otx2_cpt_common.h | 1 /* SPDX-License-Identifier: GPL-2.0-only
42 /* Take mbox id from end of CPT mbox range in AF (range 0xA00 - 0xBFF) */
50 * This message is only used between CPT PF <-> CPT VF
53 struct mbox_msghdr hdr; member
67 * Message request and response to get engine group number
72 struct mbox_msghdr hdr; member
77 struct mbox_msghdr hdr; member
84 * This messages are only used between CPT PF <-> CPT VF
87 struct mbox_msghdr hdr; member
91 struct mbox_msghdr hdr; member
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| /linux-6.14.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
| D | dp.c | 42 #define AMPERE_IED_HACK(disp) ((disp)->engine.subdev.device->card_type >= GA100)
53 *pid = BIT(outp->index); in nvkm_dp_mst_id_get()
60 int ret = nvkm_i2c_aux_acquire(outp->dp.aux); in nvkm_dp_aux_xfer()
65 ret = nvkm_i2c_aux_xfer(outp->dp.aux, false, type, addr, data, size); in nvkm_dp_aux_xfer()
66 nvkm_i2c_aux_release(outp->dp.aux); in nvkm_dp_aux_xfer()
73 outp->dp.enabled = pu; in nvkm_dp_aux_pwr()
74 nvkm_dp_enable(outp, outp->dp.enabled); in nvkm_dp_aux_pwr()
94 struct nvkm_outp *outp = lt->outp; in nvkm_dp_train_sense()
100 if (lt->repeater) in nvkm_dp_train_sense()
101 addr = DPCD_LTTPR_LANE0_1_STATUS(lt->repeater); in nvkm_dp_train_sense()
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| D | nv50.c | 49 struct nvkm_device *device = pior->disp->engine.subdev.device; in nv50_pior_clock()
58 int ret = nvkm_i2c_aux_lnk_ctl(aux, pior->dp.nr, pior->dp.bw, pior->dp.ef); in nv50_pior_dp_links()
82 struct nvkm_device *device = pior->disp->engine.subdev.device; in nv50_pior_power()
96 /* GF119 moves this information to per-head methods, which is in nv50_pior_depth()
99 if (state->head && state == &ior->asy) { in nv50_pior_depth()
100 struct nvkm_head *head = nvkm_head_find(ior->disp, __ffs(state->head)); in nv50_pior_depth()
103 struct nvkm_head_state *state = &head->asy; in nv50_pior_depth()
105 case 6: state->or.depth = 30; break; in nv50_pior_depth()
106 case 5: state->or.depth = 24; break; in nv50_pior_depth()
107 case 2: state->or.depth = 18; break; in nv50_pior_depth()
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| /linux-6.14.4/drivers/dma/bestcomm/ |
| D | bestcomm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2006-2007 Sylvain Munaut <[email protected]>
7 * ( by Andrey Volkov <avolkov@varma-el.com> )
8 * Copyright (C) 2003-2004 MontaVista, Software, Inc.
27 #define DRIVER_NAME "bestcomm-core"
31 { .compatible = "fsl,mpc5200-sram", },
32 { .compatible = "mpc5200-sram", },
49 int i, tasknum = -1; in bcom_task_alloc()
57 spin_lock(&bcom_eng->lock); in bcom_task_alloc()
60 if (!bcom_eng->tdt[i].stop) { /* we use stop as a marker */ in bcom_task_alloc()
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| /linux-6.14.4/drivers/misc/mei/ |
| D | mkhi.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2003-2022, Intel Corporation. All rights reserved.
4 * Intel Management Engine Interface (Intel MEI) Linux driver
46 struct mkhi_msg_hdr hdr; member
51 struct mkhi_msg_hdr hdr; member
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| /linux-6.14.4/drivers/infiniband/hw/hfi1/ |
| D | ruc.c | 1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright(c) 2015 - 2018 Intel Corporation.
16 return (gid->global.interface_id == id && in gid_ok()
17 (gid->global.subnet_prefix == gid_prefix || in gid_ok()
18 gid->global.subnet_prefix == IB_DEFAULT_GID_PREFIX)); in gid_ok()
31 struct rvt_qp *qp = packet->qp; in hfi1_ruc_check_hdr()
32 u8 sc5 = ibp->sl_to_sc[rdma_ah_get_sl(&qp->remote_ah_attr)]; in hfi1_ruc_check_hdr()
33 u32 dlid = packet->dlid; in hfi1_ruc_check_hdr()
34 u32 slid = packet->slid; in hfi1_ruc_check_hdr()
35 u32 sl = packet->sl; in hfi1_ruc_check_hdr()
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| D | user_sdma.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright(c) 2023 - Cornelis Networks, Inc.
4 * Copyright(c) 2015 - 2018 Intel Corporation.
27 #define num_pages(x) (1 + ((((x) - 1) & PAGE_MASK) >> PAGE_SHIFT))
43 #define PBC2LRH(x) ((((x) & 0xfff) << 2) - 4)
48 * @arr - Array to save the descriptor to.
49 * @idx - Index of the array at which the descriptor will be saved.
50 * @array_size - Size of the array arr.
51 * @dw - Update index into the header in DWs.
52 * @bit - Start bit.
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| /linux-6.14.4/sound/soc/intel/catpt/ |
| D | dsp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
19 return param == chan->device->dev; in catpt_dma_filter()
23 * Either engine 0 or 1 can be used for image loading.
24 * Align with Windows driver equivalent and stick to engine 1.
39 chan = dma_request_channel(mask, catpt_dma_filter, cdev->dev); in catpt_dma_request_config_chan()
41 dev_err(cdev->dev, "request channel failed\n"); in catpt_dma_request_config_chan()
42 return ERR_PTR(-ENODEV); in catpt_dma_request_config_chan()
54 dev_err(cdev->dev, "slave config failed: %d\n", ret); in catpt_dma_request_config_chan()
73 dev_err(cdev->dev, "prep dma memcpy failed\n"); in catpt_dma_memcpy()
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| /linux-6.14.4/drivers/crypto/marvell/octeontx/ |
| D | otx_cptpf_ucode.c | 1 // SPDX-License-Identifier: GPL-2.0
25 /* tar header as defined in POSIX 1003.1-1990. */
47 struct tar_hdr_t hdr; member
64 if (eng_grp->g->engs_num > OTX_CPT_MAX_ENGINES) { in get_cores_bmap()
66 eng_grp->g->engs_num); in get_cores_bmap()
71 if (eng_grp->engs[i].type) { in get_cores_bmap()
73 eng_grp->engs[i].bmap, in get_cores_bmap()
74 eng_grp->g->engs_num); in get_cores_bmap()
75 bmap.size = eng_grp->g->engs_num; in get_cores_bmap()
81 dev_err(dev, "No engines reserved for engine group %d\n", in get_cores_bmap()
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| /linux-6.14.4/drivers/gpu/drm/radeon/ |
| D | cik_sdma.c | 38 * sDMA - System DMA
55 * cik_sdma_get_rptr - get the current read pointer
67 if (rdev->wb.enabled) { in cik_sdma_get_rptr()
68 rptr = rdev->wb.wb[ring->rptr_offs/4]; in cik_sdma_get_rptr()
70 if (ring->idx == R600_RING_TYPE_DMA_INDEX) in cik_sdma_get_rptr()
82 * cik_sdma_get_wptr - get the current write pointer
94 if (ring->idx == R600_RING_TYPE_DMA_INDEX) in cik_sdma_get_wptr()
103 * cik_sdma_set_wptr - commit the write pointer
115 if (ring->idx == R600_RING_TYPE_DMA_INDEX) in cik_sdma_set_wptr()
120 WREG32(reg, (ring->wptr << 2) & 0x3fffc); in cik_sdma_set_wptr()
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| /linux-6.14.4/drivers/gpu/drm/amd/amdgpu/ |
| D | sdma_v6_0.c | 129 base = adev->reg_offset[GC_HWIP][0][1]; in sdma_v6_0_get_reg_offset()
133 base = adev->reg_offset[GC_HWIP][0][0]; in sdma_v6_0_get_reg_offset()
151 ret = ring->wptr & ring->buf_mask; in sdma_v6_0_ring_init_cond_exec()
159 * sdma_v6_0_ring_get_rptr - get the current read pointer
170 rptr = (u64 *)ring->rptr_cpu_addr; in sdma_v6_0_ring_get_rptr()
177 * sdma_v6_0_ring_get_wptr - get the current write pointer
187 if (ring->use_doorbell) { in sdma_v6_0_ring_get_wptr()
189 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); in sdma_v6_0_ring_get_wptr()
197 * sdma_v6_0_ring_set_wptr - commit the write pointer
205 struct amdgpu_device *adev = ring->adev; in sdma_v6_0_ring_set_wptr()
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| /linux-6.14.4/drivers/gpu/drm/nouveau/nvkm/subdev/acr/ |
| D | gp102.c | 27 #include <engine/sec2.h>
35 struct wpr_header_v1 hdr; in gp102_acr_wpr_patch() local
41 nvkm_robj(acr->wpr, offset, &hdr, sizeof(hdr)); in gp102_acr_wpr_patch()
42 wpr_header_v1_dump(&acr->subdev, &hdr); in gp102_acr_wpr_patch()
44 list_for_each_entry(lsfw, &acr->lsfw, head) { in gp102_acr_wpr_patch()
45 if (lsfw->id != hdr.falcon_id) in gp102_acr_wpr_patch()
48 nvkm_robj(acr->wpr, hdr.lsb_offset, &lsb, sizeof(lsb)); in gp102_acr_wpr_patch()
49 lsb_header_v1_dump(&acr->subdev, &lsb); in gp102_acr_wpr_patch()
51 lsfw->func->bld_patch(acr, lsb.tail.bl_data_off, adjust); in gp102_acr_wpr_patch()
55 offset += sizeof(hdr); in gp102_acr_wpr_patch()
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| /linux-6.14.4/sound/pci/emu10k1/ |
| D | emu10k1_patch.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
26 struct snd_util_memhdr *hdr, in snd_emu10k1_sample_new() argument
37 emu = rec->hw; in snd_emu10k1_sample_new()
38 if (snd_BUG_ON(!sp || !hdr)) in snd_emu10k1_sample_new()
39 return -EINVAL; in snd_emu10k1_sample_new()
41 if (sp->v.mode_flags & (SNDRV_SFNT_SAMPLE_BIDIR_LOOP | SNDRV_SFNT_SAMPLE_REVERSE_LOOP)) { in snd_emu10k1_sample_new()
42 /* should instead return -ENOTSUPP; but compatibility */ in snd_emu10k1_sample_new()
43 dev_warn(emu->card->dev, in snd_emu10k1_sample_new()
45 sp->v.sample); in snd_emu10k1_sample_new()
48 if (sp->v.mode_flags & SNDRV_SFNT_SAMPLE_8BITS) { in snd_emu10k1_sample_new()
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