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/linux-6.14.4/arch/s390/crypto/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 menu "Accelerated Cryptographic Algorithms for CPU (s390)"
6 tristate "Hash functions: SHA-384 and SHA-512"
10 SHA-384 and SHA-512 secure hash algorithms (FIPS 180)
17 tristate "Hash functions: SHA-1"
21 SHA-1 secure hash algorithm (FIPS 180)
28 tristate "Hash functions: SHA-224 and SHA-256"
32 SHA-224 and SHA-256 secure hash algorithms (FIPS 180)
39 tristate "Hash functions: SHA3-224 and SHA3-256"
43 SHA3-224 and SHA3-256 secure hash algorithms (FIPS 202)
[all …]
/linux-6.14.4/Documentation/networking/
Dscaling.rst1 .. SPDX-License-Identifier: GPL-2.0
13 multi-processor systems.
17 - RSS: Receive Side Scaling
18 - RPS: Receive Packet Steering
19 - RFS: Receive Flow Steering
20 - Accelerated Receive Flow Steering
21 - XPS: Transmit Packet Steering
28 (multi-queue). On reception, a NIC can send different packets to different
33 generally known as “Receive-side Scaling” (RSS). The goal of RSS and
35 Multi-queue distribution can also be used for traffic prioritization, but
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/linux-6.14.4/drivers/video/fbdev/core/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
50 (accelerated) version.
57 This is used by drivers that don't provide their own (accelerated)
66 (accelerated) version.
72 Allow generic frame-buffer functions to work on displays with 1, 2
82 (accelerated) version and the framebuffer is in system RAM.
89 This is used by drivers that don't provide their own (accelerated)
98 (accelerated) version and the framebuffer is in system RAM.
104 Allow generic frame-buffer to provide get_fb_unmapped_area
112 non-native endianness (e.g. Little-Endian framebuffer on a
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/linux-6.14.4/crypto/
Dpolyval-generic.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2007 Nokia Siemens Networks - Mikko Herranen <[email protected]>
12 * Code based on crypto/ghash-generic.c
15 * modulus for finite field multiplication which makes hardware accelerated
16 * implementations on little-endian machines faster. POLYVAL is used in the
17 * kernel to implement HCTR2, but was originally specified for AES-GCM-SIV
21 * Length-preserving encryption with HCTR2:
23 * AES-GCM-SIV: Nonce Misuse-Resistant Authenticated Encryption:
33 * field by computing x*REVERSE(a), where REVERSE reverses the byte-ordering of
35 * POLYVAL field by computing REVERSE(x^{-1}*a). For more information, see:
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/linux-6.14.4/Documentation/fb/
Dmatroxfb.rst16 * Most important: boot logo :-)
34 box) and matroxfb (for graphics mode). You should not compile-in vesafb
35 unless you have primary display on non-Matrox VBE2.0 device (see
43 -------------
58 -------------------------
73 ----------
86 Non-listed number can be achieved by more complicated command-line, for
93 XF{68,86}_FBDev should work just fine, but it is non-accelerated. On non-intel
97 Running another (accelerated) X-Server like XF86_SVGA works too. But (at least)
99 head, not even talking about second). Running XFree86 4.x accelerated mga
[all …]
/linux-6.14.4/include/linux/
Dif_vlan.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
23 * According to 802.3ac, the packet can be 4 bytes longer. --Klika Jan
31 * struct vlan_hdr - vlan header
41 * struct vlan_ethhdr - vlan ethernet header (ethhdr + vlan_hdr)
70 return (struct vlan_ethhdr *)skb->data; in skb_vlan_eth_hdr()
84 return dev->priv_flags & IFF_802_1Q_VLAN; in is_vlan_dev()
87 #define skb_vlan_tag_present(__skb) (!!(__skb)->vlan_all)
88 #define skb_vlan_tag_get(__skb) ((__skb)->vlan_tci)
89 #define skb_vlan_tag_get_id(__skb) ((__skb)->vlan_tci & VLAN_VID_MASK)
90 #define skb_vlan_tag_get_cfi(__skb) (!!((__skb)->vlan_tci & VLAN_CFI_MASK))
[all …]
/linux-6.14.4/drivers/net/ethernet/mellanox/mlx5/core/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
17 Core driver for low level functionality of the ConnectX-4 and
18 Connect-IB cards by Mellanox Technologies.
28 sandbox-specific client drivers.
36 Ethernet support in Mellanox Technologies ConnectX-4 NIC.
39 bool "Mellanox MLX5 ethernet accelerated receive flow steering (ARFS) support"
43 Mellanox MLX5 ethernet hardware-accelerated receive flow steering support,
61 Mellanox Technologies Ethernet Multi-Physical Function Switch (MPFS)
62 support in ConnectX NIC. MPFs is required for when multi-PF configuration
67 bool "Mellanox Technologies MLX5 SRIOV E-Switch support"
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/linux-6.14.4/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/
Dkconfig.rst1 .. SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
34 | built-in into mlx5_core.ko.
39 …g (DCB) Support <https://enterprise-support.nvidia.com/s/article/howto-auto-config-pfc-and-ets-on-…
45 | Requires CONFIG_MLX5_CORE_EN to provide an accelerated interface for the rdma
53 | Flow-based classifiers, such as those registered through
54 | `tc-flower(8)`, are processed by the device, rather than the
61 | Enables Hardware-accelerated receive flow steering (arfs) support, and ntuple filtering.
62 | https://enterprise-support.nvidia.com/s/article/howto-configure-arfs-on-connectx-4
67 | Enables :ref:`IPSec XFRM cryptography-offload acceleration <xfrm_device>`.
72 | Build support for MACsec cryptography-offload acceleration in the NIC.
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Dcounters.rst1 .. SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
13 - `Overview`_
14 - `Groups`_
15 - `Types`_
16 - `Descriptions`_
27 ----------------------------------------
29 ---------------------------------------- ---------------------------------------- |
32 | ------------------- --------------- | | ------------------- --------------- | |
34 | ------------------- --------------- | | ------------------- --------------- | |
36 | ------------------- | | ------------------- | |
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/linux-6.14.4/Documentation/devicetree/bindings/crypto/
Dintel,keembay-ocs-aes.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/intel,keembay-ocs-aes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Daniele Alessandrelli <[email protected]>
14 hardware-accelerated AES/SM4 encryption/decryption.
18 const: intel,keembay-ocs-aes
30 - compatible
31 - reg
32 - interrupts
[all …]
Dintel,keembay-ocs-hcu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/intel,keembay-ocs-hcu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Declan Murphy <[email protected]>
11 - Daniele Alessandrelli <[email protected]>
15 provides hardware-accelerated hashing and HMAC.
19 const: intel,keembay-ocs-hcu
31 - compatible
32 - reg
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/linux-6.14.4/Documentation/devicetree/bindings/leds/
Dleds-spi-byte.txt4 - one LED is controlled by a single byte on MOSI
5 - the value of the byte gives the brightness between two values (lowest to
7 - no return value is necessary (no MISO signal)
12 Depending on the compatible string some special functions (like hardware
13 accelerated blinking) might can be supported too.
16 configured in a sub-node in the device node.
19 - compatible: should be one of
20 * "ubnt,acb-spi-led" microcontroller (SONiX 8F26E611LA) based device
23 Property rules described in Documentation/devicetree/bindings/spi/spi-bus.txt
26 LED sub-node properties:
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/linux-6.14.4/drivers/net/ethernet/sfc/siena/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
9 This driver supports 10-gigabit Ethernet cards based on
13 will be called sfc-siena.
15 bool "Solarflare SFC9000-family MTD support"
19 This exposes the on-board flash and/or EEPROM as MTD devices
23 bool "Solarflare SFC9000-family hwmon support"
27 This exposes the on-board firmware-managed sensors as a
28 hardware monitor device.
30 bool "Solarflare SFC9000-family SR-IOV support"
35 features, allowing accelerated network performance in
[all …]
Dnet_driver.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2005-2013 Solarflare Communications Inc.
61 /* Checksum generation is a per-queue option in hardware, so each
62 * queue visible to the networking core is backed by two hardware TX
68 #define EFX_TXQ_TYPE_HIGHPRI 4 /* High-priority (for TC) */
70 /* HIGHPRI is Siena-only, and INNER_CSUM is EF10, so no need for both */
86 #define EFX_RX_USR_BUF_SIZE (2048 - 256)
89 * of every buffer. Otherwise, we just need to ensure 4-byte
98 /* Non-standard XDP_PACKET_HEADROOM and tailroom to satisfy XDP_REDIRECT and
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/linux-6.14.4/lib/xz/
Dxz_crc32.c1 // SPDX-License-Identifier: 0BSD
4 * CRC32 using the polynomial from IEEE-802.3
7 * Igor Pavlov <https://7-zip.org/>
12 * The fastest versions of xz_crc32() on modern CPUs without hardware
13 * accelerated CRC instruction are 3-5 times as fast as this version,
20 * STATIC_RW_DATA is used in the pre-boot environment on some architectures.
40 r = (r >> 1) ^ (poly & ~((r & 1) - 1)); in xz_crc32_init()
54 --size; in xz_crc32()
/linux-6.14.4/arch/powerpc/crypto/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 menu "Accelerated Cryptographic Algorithms for CPU (powerpc)"
14 - Little-endian
26 tristate "Hash functions: SHA-1"
29 SHA-1 secure hash algorithm (FIPS 180)
34 tristate "Hash functions: SHA-1 (SPE)"
37 SHA-1 secure hash algorithm (FIPS 180)
40 - SPE (Signal Processing Engine) extensions
43 tristate "Hash functions: SHA-224 and SHA-256 (SPE)"
48 SHA-224 and SHA-256 secure hash algorithms (FIPS 180)
[all …]
/linux-6.14.4/drivers/net/ethernet/sfc/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
20 tristate "Solarflare SFC9100/EF100-family support"
27 This driver supports 10/40-gigabit Ethernet cards based on
28 the Solarflare SFC9100-family controllers.
30 It also supports 10/25/40/100-gigabit Ethernet cards based
36 bool "Solarflare SFC9100-family MTD support"
40 This exposes the on-board flash and/or EEPROM as MTD devices
44 bool "Solarflare SFC9100-family hwmon support"
48 This exposes the on-board firmware-managed sensors as a
49 hardware monitor device.
[all …]
Dnet_driver.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2005-2013 Solarflare Communications Inc.
63 /* Checksum generation is a per-queue option in hardware, so each
64 * queue visible to the networking core is backed by two hardware TX
86 #define EFX_RX_USR_BUF_SIZE (2048 - 256)
89 * of every buffer. Otherwise, we just need to ensure 4-byte
98 /* Non-standard XDP_PACKET_HEADROOM and tailroom to satisfy XDP_REDIRECT and
111 * struct efx_buffer - A general-purpose DMA buffer
126 * struct efx_tx_buffer - buffer state for a TX descriptor
[all …]
/linux-6.14.4/drivers/soc/tegra/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 # 32-bit ARM SoCs
63 # 64-bit ARM SoCs
75 Tegra124's "4+1" Cortex-A15 CPU complex.
85 the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53
88 and providing 256 CUDA cores. It supports hardware-accelerated en-
106 combination of Denver and Cortex-A57 CPU cores and a GPU based on
107 the Pascal architecture. It contains an ADSP with a Cortex-A9 CPU
108 used for audio processing, hardware video encoders/decoders with
109 multi-format support, ISP for image capture processing and BPMP for
/linux-6.14.4/Documentation/scsi/
Dcxgb3i.rst1 .. SPDX-License-Identifier: GPL-2.0
12 (DDP) where the hardware handles the expensive byte touching operations, such
16 - iSCSI PDU digest generation and verification
23 - Direct Data Placement (DDP)
25 S3 h/w can directly place the iSCSI Data-In or Data-Out PDU's
26 payload into pre-posted final destination host-memory buffers based
27 on the Initiator Task Tag (ITT) in Data-In or Target Task Tag (TTT)
28 in Data-Out PDUs.
30 - PDU Transmit and Recovery
41 if possible, will be directly placed into the pre-posted host DDP
[all …]
/linux-6.14.4/Documentation/gpu/amdgpu/display/
Ddc-glossary.rst7 'Documentation/gpu/amdgpu/amdgpu-glossary.rst'; if you cannot find it anywhere,
16 Accelerated Processing Unit
19 Application-Specific Integrated Circuit
49 Cathode Ray Tube Controller - commonly called "Controller" - Generates
61 DC (Hardware)
108 Display Micro-Controller Unit
111 Display Micro-Controller Unit, version B
225 Transition-Minimized Differential Signaling
/linux-6.14.4/arch/s390/lib/
Dcrc32-glue.c1 // SPDX-License-Identifier: GPL-2.0
3 * CRC-32 implemented with the z/Architecture Vector Extension Facility.
8 #define KMSG_COMPONENT "crc32-vx"
15 #include "crc32-vx.h"
19 #define VX_ALIGN_MASK (VX_ALIGNMENT - 1)
24 * DEFINE_CRC32_VX() - Define a CRC-32 function using the vector extension
26 * Creates a function to perform a particular CRC-32 computation. Depending
27 * on the message buffer, the hardware-accelerated or software implementation
42 prealign = VX_ALIGNMENT - \
44 datalen -= prealign; \
[all …]
/linux-6.14.4/Documentation/ABI/testing/
Dsysfs-platform-dfl-port1 What: /sys/bus/platform/devices/dfl-port.0/id
5 Description: Read-only. It returns id of this port. One DFL FPGA device
9 What: /sys/bus/platform/devices/dfl-port.0/afu_id
13 Description: Read-only. User can program different PR bitstreams to FPGA
18 What: /sys/bus/platform/devices/dfl-port.0/power_state
22 Description: Read-only. It reports the APx (AFU Power) state, different APx
24 returns "0" - Normal / "1" - AP1 / "2" - AP2 / "6" - AP6.
26 What: /sys/bus/platform/devices/dfl-port.0/ap1_event
30 Description: Read-write. Read this file for AP1 (AFU Power State 1) event.
34 What: /sys/bus/platform/devices/dfl-port.0/ap2_event
[all …]
/linux-6.14.4/drivers/spi/
Dspi-dw-dma.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
15 #include <linux/platform_data/dma-dw.h>
19 #include "spi-dw.h"
30 if (s->dma_dev != chan->device->dev) in dw_spi_dma_chan_filter()
33 chan->private = s; in dw_spi_dma_chan_filter()
43 def_burst = dws->fifo_len / 2; in dw_spi_dma_maxburst_init()
45 ret = dma_get_slave_caps(dws->rxchan, &caps); in dw_spi_dma_maxburst_init()
51 dws->rxburst = min(max_burst, def_burst); in dw_spi_dma_maxburst_init()
52 dw_writel(dws, DW_SPI_DMARDLR, dws->rxburst - 1); in dw_spi_dma_maxburst_init()
[all …]
/linux-6.14.4/arch/m68k/include/uapi/asm/
Dbootinfo-mac.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 ** asm/bootinfo-mac.h -- Macintosh-specific boot information definitions
11 * Macintosh-specific tags (all __be32)
29 * Macintosh hardware profile data - unused, see macintosh.h for
48 #define BI_MAC_PMU 0x801f /* Mac power management / poweroff hardware */
105 #define MAC_MODEL_Q605_ACC 95 /* Q605 accelerated to 33 MHz */

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