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/linux-6.14.4/Documentation/devicetree/bindings/clock/ti/
Dti,gate-clock.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/ti/ti,gate-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments gate clock
10 - Tero Kristo <[email protected]>
13 *Deprecated design pattern: one node per clock*
15 This clock is quite much similar to the basic gate-clock [1], however,
17 is provided for this clock, the code assumes that a clockdomain
18 will be controlled instead and the corresponding hw-ops for
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/linux-6.14.4/drivers/clk/zynqmp/
Dclk-gate-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * Zynq UltraScale+ MPSoC clock controller
5 * Copyright (C) 2016-2018 Xilinx
7 * Gated clock implementation
10 #include <linux/clk-provider.h>
12 #include "clk-zynqmp.h"
15 * struct zynqmp_clk_gate - gating clock
16 * @hw: handle between common and hardware-specific interfaces
17 * @flags: hardware-specific flags
18 * @clk_id: Id of clock
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/linux-6.14.4/Documentation/devicetree/bindings/clock/
Dsprd,sc9860-clk.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/sprd,sc9860-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Spreadtrum SC9860 clock
10 - Orson Zhai <[email protected]>
11 - Baolin Wang <[email protected]>
12 - Chunyan Zhang <[email protected]>
17 - sprd,sc9860-agcp-gate
18 - sprd,sc9860-aonsecure-clk
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Dsprd,ums512-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/sprd,ums512-clk.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: UMS512 Soc clock controller
11 - Orson Zhai <[email protected]>
12 - Baolin Wang <[email protected]>
13 - Chunyan Zhang <[email protected]>
18 - sprd,ums512-apahb-gate
19 - sprd,ums512-ap-clk
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Dsprd,sc9863a-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/sprd,sc9863a-clk.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SC9863A Clock Control Unit
11 - Orson Zhai <[email protected]>
12 - Baolin Wang <[email protected]>
13 - Chunyan Zhang <[email protected]>
16 "#clock-cells":
21 - sprd,sc9863a-ap-clk
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Daltr_socfpga.txt1 Device Tree Clock bindings for Altera's SoCFPGA platform
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "altr,socfpga-pll-clock" - for a PLL clock
10 "altr,socfpga-perip-clock" - The peripheral clock divided from the
11 PLL clock.
12 "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
15 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
16 - clocks : shall be the input parent clock phandle for the clock. This is
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/linux-6.14.4/drivers/clk/bcm/
Dclk-kona.h1 /* SPDX-License-Identifier: GPL-2.0-only */
16 #include <linux/clk-provider.h>
20 /* The common clock framework uses u8 to represent a parent index */
24 #define BAD_CLK_NAME ((const char *)-1)
33 #define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
34 #define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
35 #define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag))
36 #define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag)))
40 #define ccu_policy_exists(ccu_policy) ((ccu_policy)->enable.offset != 0)
42 /* Clock field state tests */
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Dclk-kona.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include "clk-kona.h"
12 #include <linux/clk-provider.h>
28 /* Produces a mask of set bits covering a range of a 32-bit value */
31 return ((1 << width) - 1) << shift; in bitfield_mask()
53 return (u64)reg_div + ((u64)1 << div->u.s.frac_width); in scaled_div_value()
69 combined <<= div->u.s.frac_width; in scaled_div_build()
79 return (u64)div->u.fixed; in scaled_div_min()
90 return (u64)div->u.fixed; in scaled_div_max()
92 reg_div = ((u32)1 << div->u.s.width) - 1; in scaled_div_max()
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/linux-6.14.4/arch/arm/boot/dts/intel/socfpga/
Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "altr,socfpga-smp";
27 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
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/linux-6.14.4/drivers/clk/
Dclk-aspeed.c1 // SPDX-License-Identifier: GPL-2.0+
4 #define pr_fmt(fmt) "clk-aspeed: " fmt
13 #include <dt-bindings/clock/aspeed-clock.h>
15 #include "clk-aspeed.h"
49 [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
50 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
51 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
52 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
53 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */
54 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
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Dclk-ast2600.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 #define pr_fmt(fmt) "clk-ast2600: " fmt
14 #include <dt-bindings/clock/ast2600-clock.h>
16 #include "clk-aspeed.h"
20 * explicitly-configured clocks (ASPEED_CLK_HPLL and up).
81 * to control the clock enable register and the other to control the reset
85 * 2. Enable clock
89 * Consequently, if reset_idx is set, reset control is implicit: the clock
90 * consumer does not need its own reset handling, as enabling the clock will
94 * handled by using -1 as the index for the reset, and the consumer must
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Dclk-gate.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <[email protected]>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <[email protected]>
6 * Gated clock implementation
9 #include <linux/clk-provider.h>
18 * DOC: basic gatable clock which can gate and ungate its output
20 * Traits of this clock:
21 * prepare - clk_(un)prepare only ensures parent is (un)prepared
22 * enable - clk_enable and clk_disable are functional & control gating
23 * rate - inherits rate from parent. No clk_set_rate support
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/linux-6.14.4/arch/arm/boot/dts/ti/omap/
Domap3xxx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP3 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <16800000>;
15 #clock-cells = <0>;
16 compatible = "ti,mux-clock";
22 #clock-cells = <0>;
23 compatible = "ti,divider-clock";
25 ti,bit-shift = <6>;
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Domap24xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP24xx clock data
9 #clock-cells = <0>;
10 compatible = "ti,composite-mux-clock";
12 ti,bit-shift = <2>;
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
26 ti,bit-shift = <6>;
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Dam35xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP3 clock data
9 #clock-cells = <0>;
10 compatible = "ti,am35xx-gate-clock";
13 ti,bit-shift = <1>;
17 #clock-cells = <0>;
18 compatible = "ti,gate-clock";
21 ti,bit-shift = <9>;
25 #clock-cells = <0>;
26 compatible = "ti,am35xx-gate-clock";
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/linux-6.14.4/drivers/clk/sunxi/
Dclk-a20-gmac.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2013 Chen-Yu Tsai
7 * Chen-Yu Tsai <[email protected]>
10 #include <linux/clk-provider.h>
29 * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
30 * @node: &struct device_node for the clock
32 * This clock looks something like this
34 * MII TX clock from PHY >-----|___________ _________|----> to GMAC core
35 * GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
36 * Ext. 125MHz RGMII TX clk >--|__divider__/ |
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/linux-6.14.4/drivers/clk/ti/
Dgate.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP gate clock support
7 * Tero Kristo <t-[email protected]>
10 #include <linux/clk-provider.h>
17 #include "clock.h"
48 * omap36xx_gate_clk_enable_with_hsdiv_restore - enable clocks suffering
74 orig_v = ti_clk_ll_ops->clk_readl(&parent->reg); in omap36xx_gate_clk_enable_with_hsdiv_restore()
78 dummy_v ^= (1 << parent->shift); in omap36xx_gate_clk_enable_with_hsdiv_restore()
79 ti_clk_ll_ops->clk_writel(dummy_v, &parent->reg); in omap36xx_gate_clk_enable_with_hsdiv_restore()
82 ti_clk_ll_ops->clk_writel(orig_v, &parent->reg); in omap36xx_gate_clk_enable_with_hsdiv_restore()
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/linux-6.14.4/drivers/clk/imx/
Dclk-gate-exclusive.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 * struct clk_gate_exclusive - i.MX specific gate clock which is mutually
14 * exclusive with other gate clocks
16 * @gate: the parent class
17 * @exclusive_mask: mask of gate bits which are mutually exclusive to this
18 * gate clock
20 * The imx exclusive gate clock is a subclass of basic clk_gate
21 * with an addtional mask to indicate which other gate bits in the same
22 * register is mutually exclusive to this gate clock.
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Dclk-composite-7ulp.c1 // SPDX-License-Identifier: GPL-2.0+
9 #include <linux/clk-provider.h>
14 #include "../clk-fractional-divider.h"
30 struct clk_gate *gate = to_clk_gate(hw); in pcc_gate_enable() local
39 spin_lock_irqsave(gate->lock, flags); in pcc_gate_enable()
42 * with this pcc clock. in pcc_gate_enable()
44 val = readl(gate->reg); in pcc_gate_enable()
46 writel(val, gate->reg); in pcc_gate_enable()
48 spin_unlock_irqrestore(gate->lock, flags); in pcc_gate_enable()
77 struct clk_gate *gate = NULL; in imx_ulp_clk_hw_composite() local
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/linux-6.14.4/Documentation/devicetree/bindings/mfd/
Domap-usb-host.txt5 - compatible: should be "ti,usbhs-host"
6 - reg: should contain one register range i.e. start and length
7 - ti,hwmods: must contain "usb_host_hs"
11 - num-ports: number of USB ports. Usually this is automatically detected
15 - portN-mode: String specifying the port mode for port N, where N can be
18 "ehci-phy",
19 "ehci-tll",
20 "ehci-hsic",
21 "ohci-phy-6pin-datse0",
22 "ohci-phy-6pin-dpdm",
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/linux-6.14.4/include/dt-bindings/clock/
Dtegra234-clock.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
9 * @defgroup bpmp_clock_ids Clock ID's
14 /** @brief output of gate CLK_ENB_ADSP */
16 /** @brief output of gate CLK_ENB_ADSPNEON */
20 /** @brief output of gate CLK_ENB_APB2APE */
30 /** @brief output of gate CLK_ENB_CAN1_HOST */
34 /** @brief output of gate CLK_ENB_CAN2_HOST */
46 /** @brief output of gate CLK_ENB_DPAUX */
58 /** @brief clock recovered from EAVB input */
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Dtegra186-clock.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * @defgroup clock_ids Clock Identifiers
235 * @defgroup nafll_clks NAFLL clock sources
350 /** @brief output of gate CLK_ENB_FUSE */
354 * @details output of gate CLK_ENB_GPU. This output connects to the GPU
355 * pwrclk. @warning: This is almost certainly not the clock you think
356 * it is. If you're looking for the clock of the graphics engine, see
360 /** @brief output of gate CLK_ENB_PCIE */
364 /** @brief output of gate CLK_ENB_PCIE2_IOBIST */
366 /** @brief output of gate CLK_ENB_PCIERX0*/
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/linux-6.14.4/Documentation/devicetree/bindings/dma/
Dcirrus,ep9301-dma-m2p.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/cirrus,ep9301-dma-m2p.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexander Sverdlin <[email protected]>
11 - Nikita Shubin <[email protected]>
14 - $ref: dma-controller.yaml#
19 - const: cirrus,ep9301-dma-m2p
20 - items:
21 - enum:
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/linux-6.14.4/drivers/clk/samsung/
Dclk-s5pv210.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Based on clock drivers for S3C64xx and Exynos4 SoCs.
8 * Common Clock Framework support for all S5PC110/S5PV210 SoCs.
11 #include <linux/clk-provider.h>
16 #include "clk-pll.h"
18 #include <dt-bindings/clock/s5pv210.h>
20 /* S5PC110/S5PV210 clock controller register offsets */
373 /* Common clock muxes. */
386 /* S5PV210-specific clock muxes. */
431 /* S5P6442-specific clock muxes. */
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/linux-6.14.4/arch/arm64/boot/dts/sprd/
Dsharkl3.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 interrupt-parent = <&gic>;
10 #address-cells = <2>;
11 #size-cells = <2>;
14 compatible = "simple-bus";
15 #address-cells = <2>;
16 #size-cells = <2>;
20 compatible = "sprd,sc9863a-glbregs", "syscon",
21 "simple-mfd";
23 #address-cells = <1>;
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