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/linux-6.14.4/arch/x86/um/
Dtls_32.c84 * Actually, now if it wasn't flushed it gets cleared and in load_TLS()
85 * flushed to the host, which will clear it. in load_TLS()
88 if (!curr->flushed) { in load_TLS()
97 if (!(flags & O_FORCE) && curr->flushed) in load_TLS()
104 curr->flushed = 1; in load_TLS()
112 * present desc's, only if they haven't been flushed.
127 if (curr->flushed) in needs_TLS_update()
136 * On a newly forked process, the TLS descriptors haven't yet been flushed. So
149 * will remain as flushed as it was. in clear_flushed_tls()
154 curr->flushed = 0; in clear_flushed_tls()
[all …]
/linux-6.14.4/arch/powerpc/include/asm/
Dsecurity_features.h50 // The L1-D cache can be flushed with ori r30,r30,0
53 // The L1-D cache can be flushed with mtspr 882,r0 (aka SPRN_TRIG2)
76 // The L1-D cache should be flushed on MSR[HV] 1->0 transition (hypervisor to guest)
79 // The L1-D cache should be flushed on MSR[PR] 0->1 transition (kernel to userspace)
94 // The L1-D cache should be flushed when entering the kernel
97 // The L1-D cache should be flushed after user accesses from the kernel
/linux-6.14.4/tools/testing/selftests/net/forwarding/
Dbridge_mdb.sh812 # flushed when the flush command is given with no parameters.
833 check_err $? 0 "Not all entries flushed after flush all"
836 # specified port are flushed and the rest are not.
845 check_fail $? "Entry not flushed by specified port"
847 check_err $? "Entry flushed by wrong port"
849 check_err $? "Host entry flushed by wrong port"
854 check_fail $? "Host entry not flushed by specified port"
859 # specified VLAN ID are flushed and the rest are not.
869 check_fail $? "Entry not flushed by specified VLAN ID"
871 check_err $? "Entry flushed by wrong VLAN ID"
[all …]
Dbridge_locked_port.sh270 # Check that locked FDB entries are flushed from a port when MAB is disabled.
299 # FDB entry was flushed.
303 check_err $? "Regular FDB entry on first port was flushed after disabling MAB"
306 check_err $? "Regular FDB entry on second port was flushed after disabling MAB"
309 check_fail $? "Locked FDB entry on first port was not flushed after disabling MAB"
312 check_err $? "Locked FDB entry on second port was flushed after disabling MAB"
/linux-6.14.4/mm/
Dpercpu-vm.c117 * @chunk: chunk the regions to be flushed belongs to
118 * @page_start: page index of the first page to be flushed
119 * @page_end: page index of the last page to be flushed + 1
174 * @chunk: pcpu_chunk the regions to be flushed belong to
175 * @page_start: page index of the first page to be flushed
176 * @page_end: page index of the last page to be flushed + 1
245 * @chunk: pcpu_chunk the regions to be flushed belong to
246 * @page_start: page index of the first page to be flushed
247 * @page_end: page index of the last page to be flushed + 1
/linux-6.14.4/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/
Difu.json57 "PublicDescription": "Thread flushed due to TLB miss",
60 "BriefDescription": "Thread flushed due to TLB miss"
63 "PublicDescription": "Thread flushed due to reasons other than TLB miss",
66 "BriefDescription": "Thread flushed due to reasons other than TLB miss"
/linux-6.14.4/arch/x86/lib/
Dusercopy_64.c48 unsigned long flushed, dest = (unsigned long) dst; in __copy_user_flushcache() local
72 flushed = dest - (unsigned long) dst; in __copy_user_flushcache()
73 if (size > flushed && !IS_ALIGNED(size - flushed, 8)) in __copy_user_flushcache()
/linux-6.14.4/drivers/gpu/drm/i915/gt/
Dgen2_engine_cs.c52 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is in gen4_emit_flush_rcs()
53 * also flushed at 2d versus 3d pipeline switches. in gen4_emit_flush_rcs()
57 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if in gen4_emit_flush_rcs()
58 * MI_READ_FLUSH is set, and is always flushed on 965. in gen4_emit_flush_rcs()
73 * are flushed at any MI_FLUSH. in gen4_emit_flush_rcs()
/linux-6.14.4/tools/testing/selftests/net/
Dfdb_flush.sh362 # so they will be added with 'permanent' and should be flushed also.
534 # All entries should be flushed as 'state' is not an argument for flush
553 # Only entries with $dst_ip_2 should be flushed, even the rest arguments
588 # flushed.
604 log_test $? 0 "Check how many entries were flushed"
620 log_test $? 0 "Check how many entries were flushed"
636 log_test $? 0 "Check how many entries were flushed"
652 log_test $? 0 "Check how many entries were flushed"
675 # The default entry should not be flushed
/linux-6.14.4/arch/x86/um/asm/
Dprocessor_32.h17 unsigned flushed:1; member
30 { .present = 0, .flushed = 0 } }, \
/linux-6.14.4/drivers/infiniband/hw/cxgb4/
Dcq.c205 int flushed = 0; in c4iw_flush_rq() local
212 flushed++; in c4iw_flush_rq()
214 return flushed; in c4iw_flush_rq()
240 int flushed = 0; in c4iw_flush_sq() local
252 swsqe->flushed = 1; in c4iw_flush_sq()
257 flushed++; in c4iw_flush_sq()
261 wq->sq.flush_cidx += flushed; in c4iw_flush_sq()
264 return flushed; in c4iw_flush_sq()
291 swsqe->flushed = 1; in flush_completed_wrs()
362 if (qhp->wq.flushed == 1) in c4iw_flush_hw_cq()
[all …]
Drestrack.c44 if (rdma_nl_put_driver_u32(msg, "flushed", wq->flushed)) in fill_sq()
109 if (rdma_nl_put_driver_u32(msg, "flushed", sqe->flushed)) in fill_swsqe()
/linux-6.14.4/arch/x86/kernel/
Damd_nb.c246 int flushed, i; in amd_flush_garts() local
260 flushed = 0; in amd_flush_garts()
264 flushed++; in amd_flush_garts()
278 if (!flushed) in amd_flush_garts()
/linux-6.14.4/drivers/net/ppp/
Dppp_mppe.c297 * set the FLUSHED bit. This is contrary to RFC 3078, sec. 3.1. in mppe_init()
439 int flushed = MPPE_BITS(ibuf) & MPPE_BIT_FLUSHED; in mppe_decompress() local
476 if (!state->stateful && !flushed) { in mppe_decompress()
477 printk(KERN_DEBUG "mppe_decompress[%d]: FLUSHED bit not set in " in mppe_decompress()
482 if (state->stateful && ((ccount & 0xff) == 0xff) && !flushed) { in mppe_decompress()
483 printk(KERN_DEBUG "mppe_decompress[%d]: FLUSHED bit not set on " in mppe_decompress()
522 if (!flushed) { in mppe_decompress()
547 if (flushed) in mppe_decompress()
/linux-6.14.4/include/linux/
Dmm_types_task.h74 * will be flushed on all CPUs by the time that arch_tlbbatch_flush()
84 * flushed before IO is initiated or a stale TLB entry potentially
/linux-6.14.4/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_ctl.h50 * CTL registers need to be flushed after calling this function
62 * These masks are used to specify which block(s) need to be flushed
Dmdp5_ctl.c44 /* when do CTL registers need to be flushed? (mask of trigger bits) */
52 struct mdp5_ctl *pair; /* Paired CTL to be flushed together */
247 * CTL registers need to be flushed after calling this function
529 * CTL registers need to be flushed in some circumstances; if that is the
533 * Return H/W flushed bit mask.
/linux-6.14.4/arch/csky/abiv2/
Dcacheflush.c75 /* Flush this hart's I$ now, and mark it as flushed. */ in flush_icache_mm_range()
82 * flushed. in flush_icache_mm_range()
/linux-6.14.4/tools/perf/pmu-events/arch/x86/amdzen5/
Dpipeline.json59 "BriefDescription": "Percentage of dispatched ops that were flushed due to branch mispredicts.",
66 …"BriefDescription": "Percentage of dispatched ops that were flushed due to pipeline restarts (resy…
/linux-6.14.4/tools/perf/pmu-events/arch/x86/amdzen4/
Dpipeline.json58 "BriefDescription": "Fraction of dispatched ops that were flushed due to branch mispredicts.",
65 …"BriefDescription": "Fraction of dispatched ops that were flushed due to pipeline restarts (resync…
/linux-6.14.4/drivers/gpu/drm/
Ddrm_cache.c74 mb(); /*Also used after CLFLUSH so that all cache is flushed*/ in drm_cache_flush_clflush()
80 * @pages: List of pages to be flushed.
137 mb(); /*Make sure that all cache line entry is flushed*/ in drm_clflush_sg()
171 mb(); /*Ensure that every data cache line entry is flushed*/ in drm_clflush_virt_range()
/linux-6.14.4/arch/x86/kernel/acpi/
Dcstate.c41 * And caches should not be flushed by software while in acpi_processor_power_init_bm_check()
80 * And caches should not be flushed by software while in acpi_processor_power_init_bm_check()
94 * should not be flushed by software while entering C3 in acpi_processor_power_init_bm_check()
/linux-6.14.4/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_top.h35 * @split_flush_en: Allows both the paths to be flushed when master path is
36 * flushed
/linux-6.14.4/arch/riscv/mm/
Dcontext.c241 * we polluted the TLB of current HART so let's do TLB flushed in asids_init()
310 * If cache will be flushed in switch_to, no need to flush here. in flush_icache_deferred()
331 * routines in order to determine who should be flushed. in switch_mm()
/linux-6.14.4/arch/x86/include/asm/
Dtlbbatch.h10 * the PFNs being flushed..

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