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/aosp_15_r20/frameworks/native/opengl/libs/EGL/
H A DBlobCache_test.cpp8 ** http://www.apache.org/licenses/LICENSE-2.0
34 BAD_VALUE = -EINVAL,
52 ASSERT_EQ(BlobCache::InsertResult::kInserted, mBC->set("abcd", 4, "efgh", 4)); in TEST_F()
53 ASSERT_EQ(size_t(4), mBC->get("abcd", 4, buf, 4)); in TEST_F()
62 ASSERT_EQ(BlobCache::InsertResult::kInserted, mBC->set("ab", 2, "cd", 2)); in TEST_F()
63 ASSERT_EQ(BlobCache::InsertResult::kInserted, mBC->set("ef", 2, "gh", 2)); in TEST_F()
64 ASSERT_EQ(size_t(2), mBC->get("ab", 2, buf, 2)); in TEST_F()
67 ASSERT_EQ(size_t(2), mBC->get("ef", 2, buf, 2)); in TEST_F()
74 ASSERT_EQ(BlobCache::InsertResult::kInserted, mBC->set("abcd", 4, "efgh", 4)); in TEST_F()
75 ASSERT_EQ(size_t(4), mBC->get("abcd", 4, buf + 1, 4)); in TEST_F()
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/aosp_15_r20/packages/modules/NeuralNetworks/driver/cache/BlobCache/
DBlobCache_test.cpp8 ** http://www.apache.org/licenses/LICENSE-2.0
36 enum { OK = 0, BAD_VALUE = -EINVAL };
67 mBC->set("abcd", 4, "efgh", 4); in TEST_P()
68 ASSERT_EQ(size_t(4), mBC->get("abcd", 4, buf, 4)); in TEST_P()
77 mBC->set("ab", 2, "cd", 2); in TEST_P()
78 mBC->set("ef", 2, "gh", 2); in TEST_P()
79 ASSERT_EQ(size_t(2), mBC->get("ab", 2, buf, 2)); in TEST_P()
82 ASSERT_EQ(size_t(2), mBC->get("ef", 2, buf, 2)); in TEST_P()
89 mBC->set("ab", 2, "cd", 2); in TEST_P()
90 mBC->set("ef", 2, "gh", 2); in TEST_P()
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/aosp_15_r20/external/arm-neon-tests/
H A DInit.s4 ; Cortex-A8 Dhrystone example - Startup Code
26 ; Disable Cortex-A8 MMU if enabled
51 MCR p15, 0, r0, c8, c7, 0 ; Cortex-A8 I-TLB and D-TLB invalidation
54 ; Cache Invalidation code for Cortex-A8
57 ; Invalidate L1 Instruction Cache
60 TST r0, #0x3 ; Harvard Cache?
62 MCRNE p15, 0, r0, c7, c5, 0 ; Invalidate Instruction Cache
68 MOV r3, r3, LSR #23 ; Total cache levels << 1
71 MOV r10, #0 ; R10 holds current cache level << 1
72 Loop1 ADD r2, r10, r10, LSR #1 ; R2 holds cache "Set" position
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/aosp_15_r20/external/mesa3d/src/amd/compiler/
H A DREADME-ISA.md8 D.u = abs(S0.i - S1.i) + S2.u.
15 ABS_DIFF (A,B) = (A>B) ? (A-B) : (B-A)
21 `v_sad_u32(-5, 0, 0)` would return `4294967291` (`-5` interpreted as unsigned),
78 > and sent to the texture cache. Any texture or buffer resources and samplers
79 > are also sent immediately. However, write-data is not immediately sent to the
80 > texture cache.
102 ## FLAT, Scratch, Global instructions
118 GFX7-8 ISA manuals are mistaken about the available LDS size.
138 ## RDNA L0, L1 cache and DLC, GLC bits
140 The old L1 cache was renamed to L0, and a new L1 cache was added to RDNA. The
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H A Daco_assembler.cpp4 * SPDX-License-Identifier: MIT
38 : program(program_), gfx_level(program->gfx_level), symbols(symbols_) in asm_context()
52 int subvector_begin_pos = -1;
58 unsigned addr_dwords = instr->operands.size() - 3; in get_mimg_nsa_dwords()
60 if (instr->operands[3 + i].physReg() != in get_mimg_nsa_dwords()
61 instr->operands[3 + (i - 1)].physReg().advance(instr->operands[3 + (i - 1)].bytes())) in get_mimg_nsa_dwords()
62 return DIV_ROUND_UP(addr_dwords - 1, 4); in get_mimg_nsa_dwords()
70 switch (instr->opcode) { in get_vopd_opy_start()
112 uint8_t mask = get_gfx11_true16_mask(instr->opcode); in needs_vop3_gfx11()
117 if (instr->operands[i].physReg().reg() >= (256 + 128)) in needs_vop3_gfx11()
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H A Daco_print_ir.cpp4 * SPDX-License-Identifier: MIT
113 fprintf(output, "-%d]", r + size - 1); in print_physReg()
126 fprintf(output, "%d", reg - 128); in print_constant()
129 fprintf(output, "%d", 192 - reg); in print_constant()
135 case 241: fprintf(output, "-0.5"); break; in print_constant()
137 case 243: fprintf(output, "-1.0"); break; in print_constant()
139 case 245: fprintf(output, "-2.0"); break; in print_constant()
141 case 247: fprintf(output, "-4.0"); break; in print_constant()
150 print_reg_class(definition->regClass(), output); in print_definition()
151 if (definition->isPrecise()) in print_definition()
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/aosp_15_r20/external/mesa3d/src/amd/common/
H A Damd_kernel_code_t.h4 * SPDX-License-Identifier: MIT
10 //---------------------------------------------------------------------------//
12 //---------------------------------------------------------------------------//
48 ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_WIDTH) - 1)
54 ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR_WIDTH) - 1)
60 ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR_WIDTH) - 1)
66 ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR_WIDTH) - 1)
72 ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID_WIDTH) - 1)
78 ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT_WIDTH) - 1)
84 ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE_WIDTH) - 1)
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/aosp_15_r20/external/tensorflow/tensorflow/core/kernels/
H A Ddeep_conv2d.cc7 http://www.apache.org/licenses/LICENSE-2.0
57 // Element-wise products (each product is a MatMul across depth). in GetDeepConvCost()
66 const int64_t row_tiles = (out_rows + out_tile_rows - 1) / out_tile_rows; in GetDeepConvCost()
67 const int64_t col_tiles = (out_cols + out_tile_cols - 1) / out_tile_cols; in GetDeepConvCost()
208 const int64_t base_filter_rows = transform->filter_shape().rows; in operator ()()
209 const int64_t base_filter_cols = transform->filter_shape().cols; in operator ()()
212 const int64_t tile_rows = transform->input_shape().rows; in operator ()()
213 const int64_t tile_cols = transform->input_shape().cols; in operator ()()
266 // 'filter_in' into 'filter_buf', adding zero-padding as needed.
294 const int64_t num_filters = od_limit - od_start; in operator ()()
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/aosp_15_r20/external/tensorflow/tensorflow/core/kernels/mkl/
H A Dmkl_conv_ops.cc7 http://www.apache.org/licenses/LICENSE-2.0
100 return context_.fwd_pd->scratchpad_desc(); in GetScratchPadDesc()
121 // When we are using single global cache then in this case we can have in Execute()
127 // TODO(intel-tf): Create a common function and avoid the duplicate code in Execute()
128 context_.src_mem->set_data_handle( in Execute()
130 context_.filter_mem->set_data_handle( in Execute()
133 context_.bias_mem->set_data_handle( in Execute()
137 context_.bn_scale_mem->set_data_handle( in Execute()
139 context_.bn_mean_mem->set_data_handle( in Execute()
141 context_.bn_rsqrt_mem->set_data_handle( in Execute()
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H A Dmkl_qmatmul_op.cc7 http://www.apache.org/licenses/LICENSE-2.0
16 // Implements a quantized eight-bit version of the matmul operation with bias,
19 // - Input: quantized as uint8 via either MIN_FIRST or SCALE mode.
20 // SCALE mode is selected when input is guaranteed to be non-
23 // - Weight: quantized to int8 via SCALE mode.
24 // - Bias: float32/int32. For int32, it is quantized according to input and
25 // filter min-max values.
35 // With SCALE quantization (used for non-negative Af32), Qa and Au8 can be
40 // Q'a = 255.0 / (Max(Af32) - Min(Af32))
41 // A'u8 = round(Q'a * (Af32 - Min(Af32) * ones(Af32))),
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/aosp_15_r20/out/soong/
Dbuild.aosp_shiba.4.ninja2 # Module: artd-aidl-rust
3 # Variant: android_arm64_armv8-2a_cortex-a55_source
9 m.artd-aidl-rust_android_arm64_armv8-2a_cortex-a55_source.moduleDesc = //art/artd/binder:artd-aidl-…
10 m.artd-aidl-rust_android_arm64_armv8-2a_cortex-a55_source.moduleDescSuffix =
13 …out/soong/.intermediates/art/artd/binder/artd-aidl-rust/android_arm64_armv8-2a_cortex-a55_source/a…
15 …out/soong/.intermediates/art/artd/binder/artd-aidl-rust-source/gen/com/android/server/art/ArtConst…
16 …out/soong/.intermediates/art/artd/binder/artd-aidl-rust-source/gen/com/android/server/art/ArtdDexo…
17 …out/soong/.intermediates/art/artd/binder/artd-aidl-rust-source/gen/com/android/server/art/Artifact…
18 …out/soong/.intermediates/art/artd/binder/artd-aidl-rust-source/gen/com/android/server/art/Artifact…
19 …out/soong/.intermediates/art/artd/binder/artd-aidl-rust-source/gen/com/android/server/art/CopyAndR…
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/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DAMDKernelCodeT.h1 //===-- AMDGPUKernelCodeT.h - Print AMDGPU assembly code ---------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
20 //---------------------------------------------------------------------------//
22 //---------------------------------------------------------------------------//
91 …BUFFER = ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_WIDTH) - 1) << AMD_CODE_PROPE…
95 …GPR_DISPATCH_PTR = ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR_WIDTH) - 1) << AMD_CODE_PROPE…
99 …AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR = ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR_WIDTH) - …
103 …GMENT_PTR = ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR_WIDTH) - 1) << AMD_CODE_PROPE…
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/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/
H A DAMDKernelCodeT.h1 //===-- AMDGPUKernelCodeT.h - Print AMDGPU assembly code ---------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
16 //---------------------------------------------------------------------------//
18 //---------------------------------------------------------------------------//
87 …BUFFER = ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_WIDTH) - 1) << AMD_CODE_PROPE…
91 …GPR_DISPATCH_PTR = ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR_WIDTH) - 1) << AMD_CODE_PROPE…
95 …AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR = ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR_WIDTH) - …
99 …GMENT_PTR = ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR_WIDTH) - 1) << AMD_CODE_PROPE…
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H A DSIInstrFormats.td1 //===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
16 // Low bits - basic encoding information.
44 field bit FLAT = 0;
57 // High bits - other information.
70 // Most sopk treat the immediate as a signed 16-bit, however some
74 // This is an s_store_dword* instruction that requires a cache flush
76 // SMEM instructions like the cache flush ones.
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/aosp_15_r20/external/llvm/lib/Target/AMDGPU/
H A DAMDKernelCodeT.h1 //===-- AMDGPUKernelCodeT.h - Print AMDGPU assembly code ---------*- C++ -*-===//
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
21 //---------------------------------------------------------------------------//
23 //---------------------------------------------------------------------------//
92 …BUFFER = ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_WIDTH) - 1) << AMD_CODE_PROPE…
96 …GPR_DISPATCH_PTR = ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR_WIDTH) - 1) << AMD_CODE_PROPE…
100 …AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR = ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR_WIDTH) - …
104 …GMENT_PTR = ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR_WIDTH) - 1) << AMD_CODE_PROPE…
108 …_SGPR_DISPATCH_ID = ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID_WIDTH) - 1) << AMD_CODE_PROPE…
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/aosp_15_r20/external/tensorflow/tensorflow/core/util/
H A Dmkl_util.h7 http://www.apache.org/licenses/LICENSE-2.0
152 // distinguish between blocked and non-blocked formats, we have defined a new
155 // 1) FORMAT_BLOCKED: as described above, this is needed for element-wise
157 // 2) FORMAT_INVALID: for error-checking (ex. unsupported format)
160 // FORMAT_X - 1D tensor
161 // FORMAT_NC - 2D tensor
162 // FORMAT_TNC - 3D tensor
264 #define INVALID_DIM_SIZE -1
270 data_.sizes_[i] = -1;
273 data_.map_[i] = -1;
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/aosp_15_r20/external/tensorflow/tensorflow/lite/kernels/internal/
H A Dtypes.h7 http://www.apache.org/licenses/LICENSE-2.0
61 // This enumeration allows for non-default formats for the weights array
62 // of a fully-connected operator, allowing the use of special optimized
65 // Default format (flat 2D layout, the inner contiguous dimension
66 // is input_depth, the outer non-contiguous dimension is output_depth)
70 // 8-bit quantized layers.
72 // The use case we're concerned with here is: 8-bit quantization,
73 // large weights matrix that doesn't fit in cache (e.g. 4096x2048 in
74 // a key application that drove this), very small batch size (e.g. 1 -- 4).
76 // Even with 8-bit quantization of weights, the performance of memory
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/aosp_15_r20/external/mesa3d/src/amd/compiler/tests/
H A Dtest_assembler.cpp4 * SPDX-License-Identifier: MIT
6 #include <llvm/Config/llvm-config.h>
29 //~gfx[6-7]>> c7800000
30 //~gfx[6-7]! bf810000
31 //~gfx[8-9]>> s_memtime s[0:1] ; c0900000 00000000
51 bld.reset(program->create_and_insert_block());
53 program->blocks[1].linear_preds.push_back(0u);
70 bld.reset(program->create_and_insert_block());
79 bld.reset(program->create_and_insert_block());
81 program->blocks[2].linear_preds.push_back(0u);
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/aosp_15_r20/external/tensorflow/tensorflow/python/eager/
H A Dfunction.py7 # http://www.apache.org/licenses/LICENSE-2.0
15 # pylint: disable=unidiomatic-typecheck
16 """Defun decorator for defining graph-mode functions."""
74 # tf.function->autograph->->dataset->tf.function).
104 return x._type_spec # pylint: disable=protected-access
196 next_func = g._get_function(func_tag.name) # pylint: disable=protected-access
201 exc._message = error_interpolation.interpolate(message, g) # pylint: disable=protected-access
216 - `function`: _EagerDefinedFunction being created before finalizing the graph.
218 - `name`: name of the function.
219 - `graph`: Graph of the function.
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/aosp_15_r20/prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/share/man/man1/
Dx86_64-w64-mingw32-gprof.118 .\" Set up some character translations and predefined strings. \*(-- will
24 .tr \(*W-
27 . ds -- \(*W-
29 . if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch
30 . if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch
37 . ds -- \|\(em\|
73 .\" Fear. Run. Save yourself. No user-serviceable parts.
83 . ds #H ((1u-(\\\\n(.fu%2u))*.13m)
99 . ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u"
100 . ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u'
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/aosp_15_r20/external/mesa3d/docs/drivers/
H A Dasahi.rst7 -----------------
12 reverse-engineering the hardware, as glue to get at the "interesting" GPU
15 The library is only built if ``-Dtools=asahi`` is passed. It builds a single
24 -----------------
36 ``st_var`` instruction. ``st_var`` takes a *vertex output index* and a 32-bit
39 consist of a single 32-bit value or an aligned 16-bit register pair, depending
40 on whether interpolation should happen at 32-bit or 16-bit. Vertex outputs are
42 32-bit user varyings coming next with perspective, flat, and linear interpolated
43 varyings grouped in that order, then 16-bit user varyings with the same groupings,
51 .. list-table:: Ordering of vertex outputs with all outputs used
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/aosp_15_r20/external/tensorflow/tensorflow/compiler/tf2tensorrt/kernels/
H A Dtrt_engine_op.cc7 http://www.apache.org/licenses/LICENSE-2.0
66 LOG_FIRST_N(WARNING, 5) << "TF-TRT Warning: "
80 device_memory_allocator_->free(device_memory_); in ~ContextDeviceMemory()
92 device_memory_ = device_memory_allocator_->allocate( in AllocateDeviceMemory()
103 execution_context_->setDeviceMemory(device_memory_); in AllocateDeviceMemory()
192 // engine fails, enters a dummy entry into the cache_resource cache so we
255 // user-provided quantization ranges.
280 return (void*)X->flat<EnumToDataType<dt>::Type>().data(); \
284 auto tensor_type = tensor_ptr->dtype(); in GetTensorAddress()
301 flib_runtime->GetFunctionLibraryDefinition(); in FunctionDefToGraphDef()
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/aosp_15_r20/external/tensorflow/tensorflow/dtensor/cc/
H A Ddtensor_tpu_kernels.cc7 http://www.apache.org/licenses/LICENSE-2.0
57 Status status = resource_manager->Delete<ResourceT>( in DeleteIfExists()
58 resource_manager->default_container(), resource_name); in DeleteIfExists()
89 OP_REQUIRES_OK(ctx, tpu_system->Initialize(ctx, rmgr, retry_timeout, in Compute()
105 ctx->allocate_output( in Compute()
109 ctx_output->flat<int32>()(i) = core_id_output_vec[i]; in Compute()
133 // Create the subgraph compilation cache and put it in the local resource in InitializeInternal()
150 while (!tpu_platform->Initialized() && in InitializeInternal()
151 (absl::Now() - start < retry_timeout)) { in InitializeInternal()
153 init_status = tpu_platform->Initialize({}); in InitializeInternal()
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/aosp_15_r20/prebuilts/go/linux-x86/src/cmd/vendor/github.com/google/pprof/internal/report/
Dsource.go7 // http://www.apache.org/licenses/LICENSE-2.0
108 fmt.Fprintf(w, "%10s %10s (flat, cum) %s of Total\n",
118 …fmt.Fprintf(w, "%10s %10s %6d:%s\n", valueOrDot(fn.Flat, rpt), valueOrDot(fn.Cum, rpt), fn.Info.Li…
145 loc *profile.Location // Always non-nil
154 file string // For top-level function in which instruction occurs
155 line int // For top-level function in which instruction occurs
156 flat, cum int64 // Samples to report (divisor already applied) member
163 flat int64 member
171 stack []callID // Inlined call-stack
179 flat, cum int64 member
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/aosp_15_r20/external/tensorflow/tensorflow/compiler/jit/kernels/
H A Dxla_ops.cc7 http://www.apache.org/licenses/LICENSE-2.0
57 (CTX)->CtxFailureWithWarning(__FILE__, __LINE__, _s); \
133 XlaExecutableClosure value = std::move(it->second); in Consume()
153 return ctx->op_device_context() ? ctx->op_device_context()->stream() in GetStream()
161 int device_ordinal = stream ? stream->parent()->device_ordinal() in GetLaunchContext()
162 : client->default_device_ordinal(); in GetLaunchContext()
178 auto start_time = env->NowMicros(); in RunExecutable()
183 run_options.set_intra_op_thread_pool(&ctx->eigen_cpu_device()); in RunExecutable()
190 executable->Run(std::move(execution_inputs), run_options); in RunExecutable()
193 executable->RunAsync(std::move(execution_inputs), run_options); in RunExecutable()
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