| /linux-6.14.4/drivers/clk/qcom/ |
| D | ipq-cmn-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 * CMN PLL block expects the reference clock from on-board Wi-Fi block,
8 * and supplies fixed rate clocks as output to the networking hardware
13 * On the IPQ9574 SoC, there are three clocks with 50 MHZ and one clock
15 * and one clock with 353 MHZ to PPE. The other fixed rate output clocks
19 * +---------+
21 * +--+---+--+
24 * +-------+---+------+
25 * | +-------------> eth0-50mhz
27 * -------->+ +-------------> eth1-50mhz
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| D | common.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
10 #include <linux/clk-provider.h>
11 #include <linux/interconnect-clk.h>
12 #include <linux/reset-controller.h>
16 #include "clk-rcg.h"
17 #include "clk-regmap.h"
28 struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, unsigned long rate) in qcom_find_freq() argument
33 if (!f->freq) in qcom_find_freq()
36 for (; f->freq; f++) in qcom_find_freq()
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| /linux-6.14.4/arch/mips/bcm63xx/ |
| D | clk.c | 23 unsigned int rate; member
33 if (clk->set && (clk->usage++) == 0) in clk_enable_unlocked()
34 clk->set(clk, 1); in clk_enable_unlocked()
39 if (clk->set && (--clk->usage) == 0) in clk_disable_unlocked()
40 clk->set(clk, 0); in clk_disable_unlocked()
56 * Ethernet MAC "misc" clock: dma clocks and main clock on 6348
79 * Ethernet MAC clocks: only relevant on 6358, silently enable misc
80 * clocks
92 if (clk->id == 0) in enetx_set()
355 .rate = (50 * 1000 * 1000),
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| /linux-6.14.4/Documentation/devicetree/bindings/clock/ |
| D | qcom,ipq9574-cmn-pll.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <[email protected]>
11 - Luo Jie <[email protected]>
15 input clock. This reference clock is from the on-board Wi-Fi.
16 The CMN PLL supplies a number of fixed rate output clocks to
20 PLL block also outputs fixed rate clocks to GCC. The PLL's
21 primary function is to enable fixed rate output clocks for
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| D | fixed-factor-clock.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-factor-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple fixed factor rate clock sources
10 - Michael Turquette <[email protected]>
11 - Stephen Boyd <[email protected]>
16 - description:
17 If the frequency is fixed, the preferred name is 'clock-<freq>' with
19 pattern: "^clock-([0-9]+|[0-9a-z-]+)$"
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| D | samsung,s5pv210-audss-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,s5pv210-audss-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chanwoo Choi <[email protected]>
11 - Krzysztof Kozlowski <[email protected]>
12 - Sylwester Nawrocki <[email protected]>
13 - Tomasz Figa <[email protected]>
16 All available clocks are defined as preprocessor macros in
17 include/dt-bindings/clock/s5pv210-audss.h header.
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| D | samsung,s5pv210-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,s5pv210-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chanwoo Choi <[email protected]>
11 - Krzysztof Kozlowski <[email protected]>
12 - Sylwester Nawrocki <[email protected]>
13 - Tomasz Figa <[email protected]>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
18 - "xxti" - external crystal oscillator connected to XXTI and XXTO pins of
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| D | canaan,k210-clk.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/canaan,k210-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Damien Le Moal <[email protected]>
13 Canaan Kendryte K210 SoC clocks driver bindings. The clock
18 - dt-bindings/clock/k210-clk.h
22 const: canaan,k210-clk
24 clocks:
27 Phandle of the SoC 26MHz fixed-rate oscillator clock.
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| D | samsung,exynos5410-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos5410-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chanwoo Choi <[email protected]>
11 - Krzysztof Kozlowski <[email protected]>
12 - Sylwester Nawrocki <[email protected]>
13 - Tomasz Figa <[email protected]>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
18 - "fin_pll" - PLL input clock from XXTI
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| /linux-6.14.4/drivers/clk/samsung/ |
| D | clk.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
13 #include <linux/clk-provider.h>
14 #include "clk-pll.h"
15 #include "clk-cpu.h"
18 * struct samsung_clk_provider - information about clock provider
21 * @lock: maintains exclusion between callbacks for a given clock-provider
22 * @clk_data: holds clock related data like clk_hw* and number of clocks
33 * struct samsung_clock_alias - information about mux clock
54 * struct samsung_fixed_rate_clock - information about fixed-rate clock
56 * @name: name of this fixed-rate clock
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| /linux-6.14.4/Documentation/devicetree/bindings/clock/ti/ |
| D | fixed-factor-clock.txt | 1 Binding for TI fixed factor rate clock sources.
6 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
10 - compatible : shall be "ti,fixed-factor-clock".
11 - #clock-cells : from common clock binding; shall be set to 0.
12 - ti,clock-div: fixed divider.
13 - ti,clock-mult: fixed multiplier.
14 - clocks: parent clock.
17 - clock-output-names : from common clock binding.
18 - ti,autoidle-shift: bit shift of the autoidle enable bit for the clock,
20 - reg: offset for the autoidle register of this clock, see [2]
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| /linux-6.14.4/drivers/clk/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
59 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
68 generators of audio clocks.
88 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
98 multi-function device has one fixed-rate oscillator, clocked
105 This driver provides support for clocks that are controlled
115 This driver provides support for clocks that are controlled
129 be pre-programmed to support other configurations and features not yet
171 This driver supports the clocks on Bitmain BM1880 SoC.
178 This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
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| D | clk-ep93xx.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Based on a rewrite of arch/arm/mach-ep93xx/clock.c:
13 #include <linux/clk-provider.h>
20 #include <dt-bindings/clock/cirrus,ep9301-syscon.h>
94 struct clk_hw *fixed[EP93XX_FIXED_CLK_COUNT]; member
105 return container_of(clk, struct ep93xx_clk_priv, reg[clk->idx]); in ep93xx_priv_from()
110 struct ep93xx_regmap_adev *aux = priv->aux_dev; in ep93xx_clk_write()
112 aux->write(aux->map, aux->lock, reg, val); in ep93xx_clk_write()
121 regmap_read(priv->map, clk->reg, &val); in ep93xx_clk_is_enabled()
123 return !!(val & BIT(clk->bit_idx)); in ep93xx_clk_is_enabled()
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| /linux-6.14.4/Documentation/devicetree/bindings/sound/ |
| D | nvidia,tegra20-i2s.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra20-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Thierry Reding <[email protected]>
16 - Jon Hunter <[email protected]>
20 const: nvidia,tegra20-i2s
28 reset-names:
34 clocks:
40 dma-names:
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| D | nvidia,tegra20-spdif.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra20-spdif.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Thierry Reding <[email protected]>
17 - Jon Hunter <[email protected]>
20 - $ref: dai-common.yaml#
24 const: nvidia,tegra20-spdif
35 clocks:
38 clock-names:
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| D | simple-card.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/simple-card.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuninori Morimoto <[email protected]>
14 frame-master:
15 description: Indicates dai-link frame master.
18 bitclock-master:
19 description: Indicates dai-link bit clock master
22 frame-inversion:
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| /linux-6.14.4/Documentation/devicetree/bindings/ufs/ |
| D | ufs-common.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/ufs/ufs-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alim Akhtar <[email protected]>
11 - Avri Altman <[email protected]>
14 clocks: true
16 clock-names: true
18 freq-table-hz:
21 - description: Minimum frequency for given clock in Hz
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| /linux-6.14.4/drivers/clk/davinci/ |
| D | pll.c | 1 // SPDX-License-Identifier: GPL-2.0
7 * Based on arch/arm/mach-davinci/clock.c
8 * Copyright (C) 2006-2007 Texas Instruments.
9 * Copyright (C) 2008-2009 Deep Root Systems, LLC
12 #include <linux/clk-provider.h>
78 * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
85 /* From OMAP-L138 datasheet table 6-4. Units are micro seconds */
89 * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4
95 * struct davinci_pll_clk - Main PLL clock (aka PLLOUT)
117 unsigned long rate = parent_rate; in davinci_pll_recalc_rate() local
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| /linux-6.14.4/Documentation/devicetree/bindings/net/ |
| D | qcom,ipq4019-mdio.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/qcom,ipq4019-mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Robert Marko <[email protected]>
15 - enum:
16 - qcom,ipq4019-mdio
17 - qcom,ipq5018-mdio
19 - items:
20 - enum:
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| /linux-6.14.4/drivers/clk/imgtec/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
7 Enable this to support the system & CPU clocks on the MIPS Boston
9 fixed rate clocks whose rate is determined by reading a platform
|
| /linux-6.14.4/Documentation/sound/soc/ |
| D | clocking.rst | 10 ------------
17 Some master clocks (e.g. PLLs and CPU based clocks) are configurable in that
19 power). Other master clocks are fixed at a set frequency (i.e. crystals).
22 DAI Clocks
23 ----------
30 runs at exactly the sample rate (LRC = Rate).
32 Bit Clock can be generated as follows:-
34 - BCLK = MCLK / x, or
35 - BCLK = LRC * x, or
36 - BCLK = LRC * Channels * Word Size
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| /linux-6.14.4/drivers/clk/sunxi/ |
| D | clk-sunxi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include "clk-factors.h"
23 /* Maximum number of parents our clocks have */
27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
28 * PLL1 rate is calculated as follows
29 * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
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| /linux-6.14.4/include/dt-bindings/clock/ |
| D | stratix10-clock.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
9 /* fixed rate clocks */
15 /* fixed factor clocks */
21 /* PLL clocks */
26 /* Periph clocks */
61 /* Gate clocks */
|
| D | agilex-clock.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
9 /* fixed rate clocks */
16 /* PLL clocks */
31 /* fixed factor clocks */
45 /* Gate clocks */
|
| /linux-6.14.4/drivers/clk/bcm/ |
| D | clk-kona.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
16 #include <linux/clk-provider.h>
24 #define BAD_CLK_NAME ((const char *)-1)
33 #define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
34 #define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
35 #define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag))
36 #define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag)))
40 #define ccu_policy_exists(ccu_policy) ((ccu_policy)->enable.offset != 0)
44 #define policy_exists(policy) ((policy)->offset != 0)
55 #define hyst_exists(hyst) ((hyst)->offset != 0)
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