Searched +full:event +full:- +full:to +full:- +full:mhpmevent (Results 1 – 3 of 3) sorted by relevance
| /linux-6.14.4/Documentation/devicetree/bindings/perf/ |
| D | riscv,pmu.yaml | 1 # SPDX-License-Identifier: BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V SBI PMU events
10 - Atish Patra <[email protected]>
13 The SBI PMU extension allows supervisor software to configure, start and
18 The platform must provide information about PMU event to counter mappings
19 either via device tree or another way, specific to the platform.
20 Without the event to counter mappings, the SBI PMU extension cannot be used.
22 Platforms should provide information about the PMU event selector values
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| /linux-6.14.4/arch/riscv/boot/dts/allwinner/ |
| D | sun20i-d1s.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2021-2022 Samuel Holland <[email protected]>
6 #include "sunxi-d1s-t113.dtsi"
10 timebase-frequency = <24000000>;
11 #address-cells = <1>;
12 #size-cells = <0>;
19 d-cache-block-size = <64>;
20 d-cache-sets = <256>;
21 d-cache-size = <32768>;
22 i-cache-block-size = <64>;
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| /linux-6.14.4/arch/riscv/boot/dts/thead/ |
| D | th1520.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/clock/thead,th1520-clk-ap.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <3000000>;
24 riscv,isa-base = "rv64i";
25 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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