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/linux-6.14.4/Documentation/devicetree/bindings/net/
Dqca,ar71xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: ethernet-controller.yaml#
13 - Oleksij Rempel <[email protected]>
18 - items:
19 - enum:
20 - qca,ar7100-eth # Atheros AR7100
21 - qca,ar7240-eth # Atheros AR7240
22 - qca,ar7241-eth # Atheros AR7241
[all …]
Dmediatek,net.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Bianconi <[email protected]>
11 - Felix Fietkau <[email protected]>
20 - mediatek,mt2701-eth
21 - mediatek,mt7623-eth
22 - mediatek,mt7621-eth
23 - mediatek,mt7622-eth
24 - mediatek,mt7629-eth
[all …]
Dcirrus,ep9301-eth.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/cirrus,ep9301-eth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexander Sverdlin <[email protected]>
11 - Nikita Shubin <[email protected]>
14 - $ref: ethernet-controller.yaml#
19 - const: cirrus,ep9301-eth
20 - items:
21 - enum:
[all …]
Dmarvell-orion-net.txt12 set of controller registers. Each port node describes port-specific properties.
16 only one port associated. Multiple ports are implemented as multiple single-port
23 - #address-cells: shall be 1.
24 - #size-cells: shall be 0.
25 - compatible: shall be one of "marvell,orion-eth", "marvell,kirkwood-eth".
26 - reg: address and length of the controller registers.
29 - clocks: phandle reference to the controller clock.
30 - marvell,tx-checksum-limit: max tx packet size for hardware checksum.
35 - compatible: shall be one of "marvell,orion-eth-port",
36 "marvell,kirkwood-eth-port".
[all …]
Dmediatek,star-emac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek,star-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bartosz Golaszewski <[email protected]>
14 It's compliant with 802.3 standards and supports half- and full-duplex
15 modes with flow-control as well as CRC offloading and VLAN tags.
18 - $ref: ethernet-controller.yaml#
23 - mediatek,mt8516-eth
24 - mediatek,mt8518-eth
[all …]
Dstm32-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/stm32-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre Torgue <[email protected]>
12 - Christophe Roullier <[email protected]>
23 - st,stm32-dwmac
24 - st,stm32mp1-dwmac
25 - st,stm32mp13-dwmac
26 - st,stm32mp25-dwmac
[all …]
Dlpc-eth.txt4 - compatible: Should be "nxp,lpc-eth"
5 - reg: Address and length of the register set for the device
6 - interrupts: Should contain ethernet controller interrupt
9 - phy-mode: See ethernet.txt file in the same directory. If the property is
11 - use-iram: Use LPC32xx internal SRAM (IRAM) for DMA buffering
14 - mdio : specifies the mdio bus, used as a container for phy nodes according to
15 phy.txt in the same directory
21 compatible = "nxp,lpc-eth";
23 interrupt-parent = <&mic>;
26 phy-mode = "rmii";
[all …]
Dmarvell-pxa168.txt4 - compatible: should be "marvell,pxa168-eth".
5 - reg: address and length of the register set for the device.
6 - interrupts: interrupt for the device.
7 - clocks: pointer to the clock for the device.
10 - port-id: Ethernet port number. Should be '0','1' or '2'.
11 - #address-cells: must be 1 when using sub-nodes.
12 - #size-cells: must be 0 when using sub-nodes.
13 - phy-handle: see ethernet.txt file in the same directory.
18 Sub-nodes:
19 Each PHY can be represented as a sub-node. This is not mandatory.
[all …]
Dactions,owl-emac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/actions,owl-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cristian Ciocaltea <[email protected]>
15 IEEE 802.3 CSMA/CD standard, supporting both half-duplex and full-duplex
19 - $ref: ethernet-controller.yaml#
24 - const: actions,owl-emac
25 - items:
26 - enum:
[all …]
/linux-6.14.4/arch/mips/cavium-octeon/
Docteon-platform.c6 * Copyright (C) 2004-2017 Cavium, Inc.
18 #include <asm/octeon/cvmx-helper-board.h>
24 #include <asm/octeon/cvmx-uctlx-defs.h>
78 if (dev->of_node) { in octeon2_usb_clocks_start()
82 uctl_node = of_get_parent(dev->of_node); in octeon2_usb_clocks_start()
88 "refclk-frequency", &clock_rate); in octeon2_usb_clocks_start()
90 dev_err(dev, "No UCTL \"refclk-frequency\"\n"); in octeon2_usb_clocks_start()
95 "refclk-type", &clock_type); in octeon2_usb_clocks_start()
122 /* Step 3: Configure the reference clock, PHY, and HCLK */ in octeon2_usb_clocks_start()
203 * Step 4: Program the power-on reset field in the UCTL in octeon2_usb_clocks_start()
[all …]
/linux-6.14.4/arch/arm64/boot/dts/rockchip/
Drk3568-wolfvision-pf5-io-expander.dtso1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
8 /dts-v1/;
11 #include <dt-bindings/clock/rk3568-cru.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/pinctrl/rockchip.h>
17 gmac0_clkin: external-gmac0-clock {
18 compatible = "fixed-clock";
19 clock-frequency = <50000000>;
20 clock-output-names = "gmac0_clkin";
[all …]
Drk3568-fastrhino-r68s.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include "rk3568-fastrhino-r66s.dtsi"
7 compatible = "lunzn,fastrhino-r68s", "rockchip,rk3568";
15 adc-keys {
16 compatible = "adc-keys";
17 io-channels = <&saradc 0>;
18 io-channel-names = "buttons";
19 keyup-threshold-microvolt = <1800000>;
21 button-recovery {
24 press-threshold-microvolt = <1750>;
[all …]
/linux-6.14.4/arch/arm64/boot/dts/amlogic/
Dmeson-gxbb-odroidc2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-gxbb.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/sound/meson-aiu.h>
15 compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
16 model = "Hardkernel ODROID-C2";
24 stdout-path = "serial0:115200n8";
32 usb_otg_pwr: regulator-usb-pwrs {
33 compatible = "regulator-fixed";
[all …]
Dmeson-gxbb-nanopi-k2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-gxbb.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/sound/meson-aiu.h>
13 compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
22 stdout-path = "serial0:115200n8";
31 compatible = "gpio-leds";
33 led-stat {
34 label = "nanopi-k2:blue:stat";
[all …]
/linux-6.14.4/Documentation/networking/device_drivers/ethernet/freescale/dpaa2/
Dmac-phy-support.rst1 .. SPDX-License-Identifier: GPL-2.0
5 DPAA2 MAC / PHY support
11 --------
13 The DPAA2 MAC / PHY support consists of a set of APIs that help DPAA2 network
14 drivers (dpaa2-eth, dpaa2-ethsw) interact with the PHY library.
17 ---------------------------
19 Among other DPAA2 objects, the fsl-mc bus exports DPNI objects (abstracting a
20 network interface) and DPMAC objects (abstracting a MAC). The dpaa2-eth driver
26 directly by the dpaa2-eth driver or by phylink.
28 .. code-block:: none
[all …]
/linux-6.14.4/drivers/net/ethernet/sgi/
Dmeth.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * meth.c -- O2 Builtin 10/100 Ethernet driver
5 * Copyright (C) 2001-2003 Ilya Volynets
8 #include <linux/dma-mapping.h>
57 * Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
69 /* in-memory copy of MAC Control register */
72 /* in-memory copy of DMA Control register */
74 /* address of PHY, used by mdio_* functions, initialized in mdio_probe */
96 /* global, initialized in ip32-setup.c */
104 DPRINTK("Loading MAC Address: %pM\n", dev->dev_addr); in load_eaddr()
[all …]
/linux-6.14.4/drivers/net/ethernet/mediatek/
Dmtk_eth_path.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2018-2019 MediaTek Inc.
4 /* A library for configuring path from GMAC/GDM to target PHY
10 #include <linux/phy.h>
18 int (*set_path)(struct mtk_eth *eth, u64 path);
43 static int set_mux_gdm1_to_gmac1_esw(struct mtk_eth *eth, u64 path) in set_mux_gdm1_to_gmac1_esw() argument
62 if (mtk_is_netsys_v3_or_greater(eth)) in set_mux_gdm1_to_gmac1_esw()
68 mtk_m32(eth, mask, set, reg); in set_mux_gdm1_to_gmac1_esw()
70 dev_dbg(eth->dev, "path %s in %s updated = %d\n", in set_mux_gdm1_to_gmac1_esw()
76 static int set_mux_gmac2_gmac0_to_gephy(struct mtk_eth *eth, u64 path) in set_mux_gmac2_gmac0_to_gephy() argument
[all …]
/linux-6.14.4/arch/mips/boot/dts/qca/
Dar9331.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ath79-clk.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
11 #address-cells = <1>;
12 #size-cells = <0>;
22 cpuintc: interrupt-controller {
23 compatible = "qca,ar7100-cpu-intc";
25 interrupt-controller;
26 #interrupt-cells = <1>;
[all …]
/linux-6.14.4/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-stm32.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * dwmac-stm32.c - DWMAC Specific Glue layer for STM32 MCU
15 #include <linux/phy.h>
31 /* CLOCK feed to PHY*/
36 /* Ethernet PHY interface selection in register SYSCFG Configuration
37 *------------------------------------------
39 *------------------------------------------
41 *------------------------------------------
43 *------------------------------------------
45 *------------------------------------------
[all …]
/linux-6.14.4/arch/arm/boot/dts/mediatek/
Dmt7629-rfb.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
8 #include <dt-bindings/input/input.h>
13 compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
20 stdout-path = "serial0:115200n8";
23 gpio-keys {
24 compatible = "gpio-keys";
26 button-reset {
32 button-wps {
44 reg_3p3v: regulator-3p3v {
[all …]
/linux-6.14.4/arch/powerpc/boot/dts/
Dkmeter1.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * 2008-2011 DENX Software Engineering GmbH
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
28 #address-cells = <1>;
29 #size-cells = <0>;
34 d-cache-line-size = <32>; // 32 bytes
35 i-cache-line-size = <32>; // 32 bytes
36 d-cache-size = <32768>; // L1, 32K
[all …]
/linux-6.14.4/Documentation/networking/
Dstatistics.rst1 .. SPDX-License-Identifier: GPL-2.0
14 - standard interface statistics based on
16 - protocol-specific statistics; and
17 - driver-defined statistics available via ethtool.
20 -----------------------------
25 $ ip -s -s link show dev ens4u1u1
38 Note that `-s` has been specified twice to see all members of
40 If `-s` is specified once the detailed errors won't be shown.
42 `ip` supports JSON formatting via the `-j` option.
51 see `Documentation/userspace-api/netlink/intro-specs.rst`.
[all …]
/linux-6.14.4/arch/arm/boot/dts/st/
Dspear1310.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
15 compatible = "st,spear-spics-gpio";
17 st-spics,peripcfg-reg = <0x3b0>;
18 st-spics,sw-enable-bit = <12>;
19 st-spics,cs-value-bit = <11>;
20 st-spics,cs-enable-mask = <3>;
21 st-spics,cs-enable-shift = <8>;
22 gpio-controller;
23 #gpio-cells = <2>;
27 compatible = "st,spear1310-miphy";
[all …]
/linux-6.14.4/arch/arm64/boot/dts/ti/
Dk3-am654-idk.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include "k3-pinctrl.h"
17 ethernet3 = "/icssg0-eth/ethernet-ports/port@0";
18 ethernet4 = "/icssg0-eth/ethernet-ports/port@1";
19 ethernet5 = "/icssg1-eth/ethernet-ports/port@0";
20 ethernet6 = "/icssg1-eth/ethernet-ports/port@1";
[all …]
/linux-6.14.4/arch/arm64/boot/dts/mediatek/
Dmt7986b-rfb.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
12 chassis-type = "embedded";
13 compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b";
20 stdout-path = "serial0:115200n8";
33 &eth {
37 compatible = "mediatek,eth-mac";
39 phy-mode = "2500base-x";
41 fixed-link {
43 full-duplex;
[all …]

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