| /linux-6.14.4/Documentation/devicetree/bindings/display/tegra/ |
| D | nvidia,tegra20-epp.yaml | 4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-epp.yaml#
15 pattern: "^epp@[0-9a-f]+$"
19 - nvidia,tegra20-epp
20 - nvidia,tegra30-epp
21 - nvidia,tegra114-epp
38 - const: epp
62 epp@540c0000 {
63 compatible = "nvidia,tegra20-epp";
68 reset-names = "epp";
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| /linux-6.14.4/drivers/scsi/ |
| D | ppa.h | 18 * to support EPP and scatter-gather. [0.26-athena]
22 * Fixed EPP to handle "software" changing of EPP port data direction.
23 * Chased down EPP timeouts
32 * Fixed id_probe for EPP 1.9 chipsets (misdetected as EPP 1.7)
38 * Hack and slash at the init code (EPP device check routine)
98 #define PPA_EPP_8 3 /* EPP mode, 8 bit */
99 #define PPA_EPP_16 4 /* EPP mode, 16 bit */
100 #define PPA_EPP_32 5 /* EPP mode, 32 bit */
108 "EPP 8 bit",
109 "EPP 16 bit",
[all …]
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| D | imm.h | 37 * Now have byte mode working (only EPP and ECP to go now... :=)
40 * Thirty minutes of further coding results in EPP working on my machine.
91 #define IMM_EPP_8 3 /* EPP mode, 8 bit */
92 #define IMM_EPP_16 4 /* EPP mode, 16 bit */
93 #define IMM_EPP_32 5 /* EPP mode, 32 bit */
101 [IMM_EPP_8] = "EPP 8 bit",
102 [IMM_EPP_16] = "EPP 16 bit",
103 [IMM_EPP_32] = "EPP 32 bit",
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| D | imm.c | 61 "2 = SPP 8-bit, 3 = EPP 8-bit, 4 = EPP 16-bit, 5 = EPP 32-bit");
272 * Clear EPP timeout bit.
479 * 0010 00aa Select device aa in EPP Winbond mode in imm_cpp()
480 * 0010 10aa Select device aa in EPP mode in imm_cpp()
531 return imm_cpp(ppb, 0x28); /* Select device 0 in EPP mode */ in imm_connect()
753 printk("imm: BUS BUSY - EPP timeout detected\n"); in imm_interrupt()
1019 /* This routine looks for a device and then attempts to use EPP in device_check()
1020 to send a command. If all goes as planned then EPP is available. */ in device_check()
1028 /* Attempt to use EPP for Test Unit Ready */ in device_check()
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| /linux-6.14.4/tools/power/cpupower/utils/ |
| D | cpupower-set.c | 21 {"epp", required_argument, NULL, 'e'},
43 int epp:1; in cmd_set() member
51 char epp[30], mode[20]; in cmd_set() local
80 if (params.epp) in cmd_set()
82 if (sscanf(optarg, "%29s", epp) != 1) { in cmd_set()
86 params.epp = 1; in cmd_set()
157 if (params.epp) { in cmd_set()
158 ret = cpupower_set_epp(cpu, epp); in cmd_set()
161 "Error setting epp value on CPU %d\n", cpu); in cmd_set()
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| D | cpufreq-info.c | 425 /* --epp / -z */
429 char *epp; in get_epp() local
431 epp = cpufreq_get_energy_performance_preference(cpu); in get_epp()
432 if (!epp) in get_epp()
435 printf(_(" energy performance preference: %s\n"), epp); in get_epp()
437 cpufreq_put_energy_performance_preference(epp); in get_epp()
525 {"epp", no_argument, NULL, 'z'},
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| /linux-6.14.4/drivers/cpufreq/ |
| D | amd-pstate-trace.h | 90 u8 epp,
98 epp,
106 __field(u8, epp)
115 __entry->epp = epp;
121 TP_printk("cpu%u: [%hhu<->%hhu]/%hhu, epp=%hhu, boost=%u",
126 (u8)__entry->epp,
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| D | amd-pstate.c | 98 * AMD Energy Preference Performance (EPP)
99 * The EPP is used in the CCLK DPM controller to drive
101 * short periods of activity. EPP values will be utilized for
103 * display strings corresponding to EPP index in the
212 u64 epp; in shmem_get_epp() local
215 ret = cppc_get_epp_perf(cpudata->cpu, &epp); in shmem_get_epp()
221 return FIELD_GET(AMD_CPPC_EPP_PERF_MASK, epp); in shmem_get_epp()
225 u8 des_perf, u8 max_perf, u8 epp, bool fast_switch) in msr_update_perf() argument
236 value |= FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, epp); in msr_update_perf()
252 WRITE_ONCE(cpudata->epp_cached, epp); in msr_update_perf()
[all …]
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| D | intel_pstate.c | 211 * (EPP) or energy performance bias (EPB),
213 * @epp_policy: Last saved policy used to set EPP/EPB
632 s16 epp; in intel_pstate_get_epp() local
637 * MSR_HWP_REQUEST, so need to read and get EPP. in intel_pstate_get_epp()
640 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, in intel_pstate_get_epp()
642 if (epp) in intel_pstate_get_epp()
643 return epp; in intel_pstate_get_epp()
645 epp = (hwp_req_data >> 24) & 0xff; in intel_pstate_get_epp()
647 /* When there is no EPP present, HWP uses EPB settings */ in intel_pstate_get_epp()
648 epp = intel_pstate_get_epb(cpu_data); in intel_pstate_get_epp()
[all …]
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| /linux-6.14.4/tools/power/x86/x86_energy_perf_policy/ |
| D | x86_energy_perf_policy.8 | 14 .RB "field: \-\-all | \-\-epb | \-\-hwp-epp | \-\-hwp-min | \-\-hwp-max | \-\-hwp-desired"
46 Energy_Performance_Preference (EPP) field in
109 VALUE STRING EPB EPP
122 \fB-a, --all value-string\fP Sets all EPB and EPP and HWP limit fields to the value associated with
133 \fB-P, --hwp-epp\fP set HWP.EPP per-core or per-package.
185 cpu0: HWP_REQ: min 6 max 35 des 0 epp 128 window 0x0 (0*10^0us) use_pkg 0
188 cpu1: HWP_REQ: min 6 max 35 des 0 epp 128 window 0x0 (0*10^0us) use_pkg 0
191 cpu2: HWP_REQ: min 6 max 35 des 0 epp 128 window 0x0 (0*10^0us) use_pkg 0
194 cpu3: HWP_REQ: min 6 max 35 des 0 epp 128 window 0x0 (0*10^0us) use_pkg 0
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| /linux-6.14.4/include/uapi/linux/ |
| D | parport.h | 58 #define PARPORT_MODE_EPP (1<<2) /* Hardware EPP. */
65 Nibble mode, byte mode, ECP, ECPRLE and EPP are their own
76 #define IEEE1284_MODE_EPPSL (1<<11) /* EPP 1.7 */
93 #define PARPORT_EPP_FAST_32 PARPORT_EPP_FAST /* 32-bit EPP transfers */
94 #define PARPORT_EPP_FAST_16 (1<<2) /* 16-bit EPP transfers */
95 #define PARPORT_EPP_FAST_8 (1<<3) /* 8-bit EPP transfers */
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| /linux-6.14.4/arch/sparc/include/asm/ |
| D | ns87303.h | 40 #define PTR_LEVEL_IRQ 0x80 /* When not ECP/EPP: Use level IRQ */
41 #define PTR_LPT_REG_DIR 0x80 /* When ECP/EPP: LPT CTR controls direction */
46 #define FCR_ZWS_ENA 0x20 /* Enable short host read/write in ECP/EPP */
50 #define PCR_EPP_IEEE 0x02 /* Enable EPP Version 1.9 (IEEE 1284) */
58 #define TUP_EPP_TIMO 0x02 /* Enable EPP timeout IRQ */
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| /linux-6.14.4/drivers/ata/pata_parport/ |
| D | dstr.c | 21 * 2 8-bit EPP mode
22 * 3 EPP-16
23 * 4 EPP-32
209 char *mode_string[5] = { "4-bit", "8-bit", "EPP-8", "EPP-16", "EPP-32" }; in dstr_log_adapter()
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| D | epia.c | 25 * 3 8-bit EPP mode
26 * 4 16-bit EPP
27 * 5 32-bit EPP
99 * some EPP counters ... currently we know about 3 different block
284 char *mode[6] = { "4-bit", "5/3", "8-bit", "EPP-8", "EPP-16", "EPP-32"}; in epia_log_adapter()
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| D | bpck6.c | 328 /* EPP */ in bpck6_open()
357 /* EPP */ in bpck6_deselect()
401 return 5; /* Can do EPP */ in bpck6_test_port()
436 char *mode_string[5] = { "4-bit", "8-bit", "EPP-8", "EPP-16", "EPP-32" }; in bpck6_log_adapter()
447 .epp_first = 2, /* 2-5 use epp (need 8 ports) */
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| D | on26.c | 21 * 2 8-bit EPP mode
22 * 3 EPP-16
23 * 4 EPP-32
288 char *mode_string[5] = { "4-bit", "8-bit", "EPP-8", "EPP-16", "EPP-32" }; in on26_log_adapter()
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| D | comm.c | 22 * 2 8-bit EPP mode
179 char *mode_string[5] = { "4-bit", "8-bit", "EPP-8", "EPP-16", "EPP-32" }; in comm_log_adapter()
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| D | frpw.c | 270 char *mode[6] = { "4-bit", "8-bit", "EPP", "EPP-8", "EPP-16", "EPP-32"}; in frpw_log_adapter()
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| /linux-6.14.4/drivers/net/ethernet/sfc/siena/ |
| D | siena_sriov.c | 406 struct efx_endpoint_page *epp; in __efx_siena_sriov_push_vf_status() local
438 list_for_each_entry(epp, &nic_data->local_page_list, link) { in __efx_siena_sriov_push_vf_status()
447 copy[pos].from_addr = epp->addr; in __efx_siena_sriov_push_vf_status()
1087 struct efx_endpoint_page *epp; in efx_siena_sriov_peer_work() local
1126 epp = kmalloc(sizeof(*epp), GFP_KERNEL); in efx_siena_sriov_peer_work()
1127 if (!epp) in efx_siena_sriov_peer_work()
1129 epp->ptr = dma_alloc_coherent( in efx_siena_sriov_peer_work()
1131 &epp->addr, GFP_KERNEL); in efx_siena_sriov_peer_work()
1132 if (!epp->ptr) { in efx_siena_sriov_peer_work()
1133 kfree(epp); in efx_siena_sriov_peer_work()
[all …]
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| /linux-6.14.4/drivers/parport/ |
| D | ieee1284_ops.c | 14 * Software emulated EPP fixes, Fred Barnes, 04/2001.
705 * EPP functions. *
708 /* EPP mode, forward channel, data. */
716 /* set EPP idle state (just to make sure) with strobe low */ in parport_ieee1284_epp_write_data()
752 /* EPP mode, reverse channel, data. */
760 /* set EPP idle state (just to make sure) with strobe high */ in parport_ieee1284_epp_read_data()
796 /* EPP mode, forward channel, addresses. */
804 /* set EPP idle state (just to make sure) with strobe low */ in parport_ieee1284_epp_write_addr()
840 /* EPP mode, reverse channel, addresses. */
848 /* Set EPP idle state (just to make sure) with strobe high */ in parport_ieee1284_epp_read_addr()
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| D | parport_pc.c | 31 * base+3 EPP address
32 * base+4 EPP data
204 * Clear TIMEOUT BIT in EPP MODE
300 /* EPP timeout should never occur... */ in parport_pc_epp_read_data()
301 … printk(KERN_DEBUG "%s: EPP timeout occurred while talking to w91284pic (should not have done)\n", in parport_pc_epp_read_data()
329 /* EPP timeout */ in parport_pc_epp_read_data()
974 "EPP and SPP", in show_parconfig_smsc37c669()
976 "ECP and EPP" }; in show_parconfig_smsc37c669()
1009 pr_info("SMSC LPT Config: Port mode=%s, EPP version =%s\n", in show_parconfig_smsc37c669()
1054 "EPP-1.9 and SPP", in show_parconfig_winbond()
[all …]
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| D | parport_ip32.c | 19 * Hardware SPP (a.k.a. compatibility), EPP, and ECP modes are
30 * EPP and ECP mode need to be tested. I currently do not own any
42 * This chip supports SPP, bidirectional, EPP and ECP modes. It has a 16 byte
141 * @eppAddr: EPP Address Register
142 * @eppData0: EPP Data Register 0
143 * @eppData1: EPP Data Register 1
144 * @eppData2: EPP Data Register 2
145 * @eppData3: EPP Data Register 3
179 #define DSR_TIMEOUT (1U << 0) /* EPP timeout */
327 "ECP", "EPP", "???", in parport_ip32_dump_state()
[all …]
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| D | parport_gsc.c | 47 * Clear TIMEOUT BIT in EPP MODE
138 * first clear an eventually pending EPP timeout in parport_SPP_supported()
140 * that does not even respond to SPP cycles if an EPP in parport_SPP_supported()
299 printmode(EPP); in parport_gsc_probe_port()
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| /linux-6.14.4/drivers/accel/ivpu/ |
| D | ivpu_hw_btrs.c | 214 u16 epp; member
229 val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1, EPP, PLL_EPP_DEFAULT, val); in wp_request_mtl()
252 val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1, EPP, wp->epp, val); in wp_request_lnl()
303 wp->epp = 0; in prepare_wp_request()
308 wp->epp = enable ? PLL_EPP_DEFAULT : 0; in prepare_wp_request()
337 ivpu_dbg(vdev, PM, "PLL workpoint request: %lu MHz, config: 0x%x, epp: 0x%x, cdyn: 0x%x\n", in ivpu_hw_btrs_wp_drive()
338 pll_ratio_to_dpu_freq(vdev, wp.target) / HZ_PER_MHZ, wp.cfg, wp.epp, wp.cdyn); in ivpu_hw_btrs_wp_drive()
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| /linux-6.14.4/Documentation/devicetree/bindings/clock/ |
| D | zynq-7000.txt | 1 Device Tree Clock bindings for the Zynq 7000 EPP
3 The Zynq EPP has several different clk providers, each with there own bindings.
|