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Searched +full:dual +full:- +full:lvds +full:- +full:odd +full:- +full:pixels (Results 1 – 19 of 19) sorted by relevance

/linux-6.14.4/Documentation/devicetree/bindings/display/
Dlvds-dual-ports.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/lvds-dual-ports.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Dual-link LVDS Display Common Properties
10 - Liu Ying <[email protected]>
13 Common properties for LVDS displays with dual LVDS links. Extend LVDS display
14 common properties defined in lvds.yaml.
16 Dual-link LVDS displays receive odd pixels and even pixels separately from
17 the dual LVDS links. One link receives odd pixels and the other receives
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/linux-6.14.4/Documentation/devicetree/bindings/display/panel/
Dadvantech,idk-2121wr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/advantech,idk-2121wr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Advantech IDK-2121WR 21.5" Full-HD dual-LVDS panel
10 - Lad Prabhakar <prabhakar.mahadev-[email protected]>
11 - Thierry Reding <[email protected]>
14 The IDK-2121WR from Advantech is a Full-HD dual-LVDS panel.
15 A dual-LVDS interface is a dual-link connection with even pixels traveling
16 on one link, and with odd pixels traveling on the other link.
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Dpanel-simple-lvds-dual-ports.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-simple-lvds-dual-ports.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple LVDS panels with one power supply and dual LVDS ports
10 - Liu Ying <[email protected]>
11 - Thierry Reding <[email protected]>
12 - Sam Ravnborg <[email protected]>
15 This binding file is a collection of the LVDS panels that
16 has dual LVDS ports and requires only a single power-supply.
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/linux-6.14.4/drivers/gpu/drm/
Ddrm_of.c1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <linux/media-bus-format.h>
25 * drm_of_crtc_port_mask - find the mask of a registered CRTC by port OF node
39 if (tmp->port == port) in drm_of_crtc_port_mask()
50 * drm_of_find_possible_crtcs - find the possible CRTCs for an encoder port
83 * drm_of_component_match_add - Add a component helper OF node match rule
101 * drm_of_component_probe - Generic probe function for a component based master
121 if (!dev->of_node) in drm_of_component_probe()
122 return -EINVAL; in drm_of_component_probe()
129 port = of_parse_phandle(dev->of_node, "ports", i); in drm_of_component_probe()
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/linux-6.14.4/Documentation/devicetree/bindings/display/bridge/
Dite,it6263.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ITE IT6263 LVDS to HDMI converter
10 - Liu Ying <[email protected]>
13 The IT6263 is a high-performance single-chip De-SSC(De-Spread Spectrum) LVDS
14 to HDMI converter. Combined with LVDS receiver and HDMI 1.4a transmitter,
15 the IT6263 supports LVDS input and HDMI 1.4 output by conversion function.
16 The built-in LVDS receiver can support single-link and dual-link LVDS inputs,
17 and the built-in HDMI transmitter is fully compliant with HDMI 1.4a/3D, HDCP
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Dthine,thc63lvd1024.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Thine Electronics THC63LVD1024 LVDS Decoder
10 - Jacopo Mondi <[email protected]>
11 - Laurent Pinchart <[email protected]>
14 The THC63LVD1024 is a dual link LVDS receiver designed to convert LVDS
15 streams to parallel data outputs. The chip supports single/dual input/output
16 modes, handling up to two LVDS input streams and up to two digital CMOS/TTL
19 Single or dual operation mode, output data mapping and DDR output modes are
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Dfsl,imx8qxp-ldb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qm/qxp LVDS Display Bridge
10 - Liu Ying <[email protected]>
13 The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels.
23 LDB split mode to support a dual link LVDS display. The channel indexes
24 have to be different. Channel0 outputs odd pixels and channel1 outputs
25 even pixels.
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/linux-6.14.4/arch/arm64/boot/dts/freescale/
Dimx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi"
12 dual-lvds-even-pixels;
15 remote-endpoint = <&ldb_lvds_ch1>;
21 dual-lvds-odd-pixels;
24 remote-endpoint = <&ldb_lvds_ch0>;
34 remote-endpoint = <&it6263_lvds_link2>;
40 remote-endpoint = <&it6263_lvds_link1>;
Dimx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi"
12 dual-lvds-odd-pixels;
15 remote-endpoint = <&ldb_lvds_ch0>;
21 dual-lvds-even-pixels;
24 remote-endpoint = <&ldb_lvds_ch1>;
34 remote-endpoint = <&it6263_lvds_link1>;
40 remote-endpoint = <&it6263_lvds_link2>;
Dimx8mp-evk-mx8-dlvds-lcd1.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 panel-lvds {
13 power-supply = <&reg_vext_3v3>;
15 panel-timing {
16 clock-frequency = <148500000>;
19 hfront-porch = <130>;
20 hback-porch = <70>;
21 hsync-len = <30>;
22 vfront-porch = <5>;
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Dimx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtso1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright (c) 2023 TQ-Systems GmbH <[email protected]-group.com>,
4 * D-82229 Seefeld, Germany.
8 /dts-v1/;
11 #include <dt-bindings/clock/imx8mp-clock.h>
14 compatible = "tq,imx8mp-tqma8mpql-mba8mpxl", "tq,imx8mp-tqma8mpql", "fsl,imx8mp";
26 #address-cells = <1>;
27 #size-cells = <0>;
31 dual-lvds-odd-pixels;
34 remote-endpoint = <&ldb_lvds_ch0>;
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/linux-6.14.4/arch/arm64/boot/dts/renesas/
Dr8a774c0-ek874-idk-2121wr.dts1 // SPDX-License-Identifier: GPL-2.0
4 * connected to an Advantech IDK-2121WR 21.5" LVDS panel
9 #include "r8a774c0-ek874.dts"
13 compatible = "pwm-backlight";
16 brightness-levels = <0 4 8 16 32 64 128 255>;
17 default-brightness-level = <6>;
19 power-supply = <&reg_12p0v>;
20 enable-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
23 panel-lvds {
24 compatible = "advantech,idk-2121wr", "panel-lvds";
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/linux-6.14.4/drivers/gpu/drm/renesas/rcar-du/
Drcar_lvds.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car LVDS Encoder
5 * Copyright (C) 2013-2018 Renesas Electronics Corporation
13 #include <linux/media-bus-format.h>
50 #define RCAR_LVDS_QUIRK_LANES BIT(0) /* LVDS lanes 1 and 3 inverted */
54 #define RCAR_LVDS_QUIRK_DUAL_LINK BIT(4) /* Supports dual-link operation */
59 void (*pll_setup)(struct rcar_lvds *lvds, unsigned int freq);
86 static u32 rcar_lvds_read(struct rcar_lvds *lvds, u32 reg) in rcar_lvds_read() argument
88 return ioread32(lvds->mmio + reg); in rcar_lvds_read()
91 static void rcar_lvds_write(struct rcar_lvds *lvds, u32 reg, u32 data) in rcar_lvds_write() argument
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/linux-6.14.4/include/drm/
Ddrm_of.h1 /* SPDX-License-Identifier: GPL-2.0 */
23 * enum drm_lvds_dual_link_pixels - Pixel order of an LVDS dual-link connection
24 * @DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS: Even pixels are expected to be generated
25 * from the first port, odd pixels from the second port
26 * @DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS: Odd pixels are expected to be generated
27 * from the first port, even pixels from the second port
90 return -EINVAL; in drm_of_component_probe()
97 return -EINVAL; in drm_of_encoder_active_endpoint()
104 return -EINVAL; in drm_of_find_panel_or_bridge()
111 return -EINVAL; in drm_of_lvds_get_dual_link_pixel_order()
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Ddrm_bridge.h49 * enum drm_bridge_attach_flags - Flags for &drm_bridge_funcs.attach
60 * struct drm_bridge_funcs - drm_bridge control functions
111 * to look at anything else but the passed-in mode, and validate it
112 * against configuration-invariant hardware constraints. Any further
370 * non-NULL).
529 * DRM_BRIDGE_OP_DETECT flag in their &drm_bridge->ops.
543 * The @get_modes callback is mostly intended to support non-probeable
546 * &drm_bridge_funcs->edid_read callback instead.
549 * DRM_BRIDGE_OP_MODES flag in their &drm_bridge->ops.
577 * DRM_BRIDGE_OP_EDID flag in their &drm_bridge->ops.
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/linux-6.14.4/drivers/gpu/drm/bridge/
Dti-sn65dsi83.c1 // SPDX-License-Identifier: GPL-2.0
6 * - SN65DSI83
7 * = 1x Single-link DSI ~ 1x Single-link LVDS
8 * - Supported
9 * - Single-link LVDS mode tested
10 * - SN65DSI84
11 * = 1x Single-link DSI ~ 2x Single-link or 1x Dual-link LVDS
12 * - Supported
13 * - Dual-link LVDS mode tested
14 * - 2x Single-link LVDS mode unsupported
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Dlontium-lt9211.c1 // SPDX-License-Identifier: GPL-2.0
6 * 2xDSI/2xLVDS/1xDPI -> 2xDSI/2xLVDS/1xDPI
8 * 1xDSI -> 1xLVDS
17 #include <linux/media-bus-format.h>
40 /* DSI lane count - 0 means 4 lanes ; 1, 2, 3 means 1, 2, 3 lanes. */
106 return drm_bridge_attach(bridge->encoder, ctx->panel_bridge, in lt9211_attach()
107 &ctx->bridge, flags); in lt9211_attach()
116 ret = regmap_bulk_read(ctx->regmap, REG_CHIPID0, chipid, 3); in lt9211_read_chipid()
118 dev_err(ctx->dev, "Failed to read Chip ID: %d\n", ret); in lt9211_read_chipid()
125 dev_err(ctx->dev, "Unknown Chip ID: 0x%02x 0x%02x 0x%02x\n", in lt9211_read_chipid()
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/linux-6.14.4/drivers/gpu/drm/bridge/imx/
Dimx8qxp-ldb.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/media-bus-format.h>
26 #include "imx-ldb-helper.h"
36 #define DRIVER_NAME "imx8qxp-ldb"
69 phy_cfg->bits_per_lane_and_dclk_cycle = 7; in imx8qxp_ldb_set_phy_cfg()
70 phy_cfg->lanes = 4; in imx8qxp_ldb_set_phy_cfg()
73 phy_cfg->differential_clk_rate = di_clk / 2; in imx8qxp_ldb_set_phy_cfg()
74 phy_cfg->is_slave = !imx8qxp_ldb->companion; in imx8qxp_ldb_set_phy_cfg()
76 phy_cfg->differential_clk_rate = di_clk; in imx8qxp_ldb_set_phy_cfg()
77 phy_cfg->is_slave = false; in imx8qxp_ldb_set_phy_cfg()
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/linux-6.14.4/drivers/gpu/drm/i915/display/
Dintel_display.c2 * Copyright © 2006-2007 Intel Corporation
27 #include <linux/dma-resv.h>
161 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != in vlv_get_cck_clock()
175 if (dev_priv->hpll_freq == 0) in vlv_get_cck_clock_hpll()
176 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); in vlv_get_cck_clock_hpll()
178 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); in vlv_get_cck_clock_hpll()
190 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", in intel_update_czclk()
193 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", in intel_update_czclk()
194 dev_priv->czclk_freq); in intel_update_czclk()
199 return (crtc_state->active_planes & in is_hdr_mode()
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