| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| D | link_dp_training_dpia.c | 66 DPIA_TS_UFP_DONE = 0xff /* Done training DPTX-to-DPIA hop. */
277 * - CR for the first hop (DPTX-to-DPIA) is assumed to be successful.
314 /* DPTX-to-DPIA */ in dpia_training_cr_non_transparent()
571 * - EQ for the first hop (DPTX-to-DPIA) is assumed to be successful.
609 /* DPTX-to-DPIA equalization always successful. */ in dpia_training_eq_non_transparent()
850 * (DPTX-to-DPIA) and last hop (DPRX).
868 if (hop == repeater_cnt) { /* DPTX-to-DPIA */ in dpia_training_end()
870 * DPTX-to-DPIA hop trained. No DPCD write needed for first hop. in dpia_training_end()
1007 /* Train each hop in turn starting with the one closest to DPTX. in dpia_perform_link_training()
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| D | link_dp_dpia_bw.c | 325 /* Send request acknowledgment to Turn ON DPTX support */ in link_dp_dpia_set_dptx_usb4_bw_alloc_support()
334 DC_LOG_DEBUG("%s: FAILURE Enabling DPtx BW Allocation Mode Support for link(%d)\n", in link_dp_dpia_set_dptx_usb4_bw_alloc_support()
337 // SUCCESS Enabled DPtx BW Allocation Mode Support in link_dp_dpia_set_dptx_usb4_bw_alloc_support()
338 DC_LOG_DEBUG("%s: SUCCESS Enabling DPtx BW Allocation Mode Support for link(%d)\n", in link_dp_dpia_set_dptx_usb4_bw_alloc_support()
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| D | link_dp_training.c | 956 * AUX_RD_INTERVAL for DPTX-to-DPIA hop. in configure_lttpr_mode_non_transparent()
1512 * If the upstream DPTX and downstream DPRX both support TPS4, in dp_transition_to_video_idle()
1576 * Per DP specs starting from here, DPTX device shall not issue in dp_perform_link_training()
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| /linux-6.14.4/drivers/gpu/drm/rockchip/ |
| D | cdn-dp-reg.h | 114 /* dptx phy addr */
123 /* dptx hpd addr */
151 /* dptx stream addr */
169 /* dptx glbl addr */
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| D | cdn-dp-core.c | 49 #define CDN_DP_FIRMWARE "rockchip/dptx.bin"
154 int dptx; in cdn_dp_get_port_lanes() local
157 dptx = extcon_get_state(edev, EXTCON_DISP_DP); in cdn_dp_get_port_lanes()
158 if (dptx > 0) { in cdn_dp_get_port_lanes()
761 dp->dptx_rst = devm_reset_control_get(dev, "dptx"); in cdn_dp_parse_dt()
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| /linux-6.14.4/Documentation/devicetree/bindings/sound/ |
| D | mt8195-mt6359.yaml | 60 mediatek,dptx-codec:
135 mediatek,dptx-codec: false
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| /linux-6.14.4/drivers/gpu/drm/bridge/analogix/ |
| D | Makefile | 2 analogix_dp-objs := analogix_dp_core.o analogix_dp_reg.o analogix-i2c-dptx.o
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| D | analogix-i2c-dptx.c | 14 #include "analogix-i2c-dptx.h"
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| D | analogix-anx78xx.h | 9 #include "analogix-i2c-dptx.h"
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| D | analogix-anx6345.c | 31 #include "analogix-i2c-dptx.h"
58 /* I2C Slave addresses of ANX6345 are mapped as DPTX and SYS */
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| /linux-6.14.4/drivers/gpu/drm/mediatek/ |
| D | Kconfig | 25 tristate "DRM DPTX Support for MediaTek SoCs"
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| /linux-6.14.4/sound/soc/mediatek/mt8188/ |
| D | mt8188-dai-etdm.c | 367 else if (!strncmp(name, "DPTX", strlen("DPTX"))) in get_etdm_id_by_name()
1344 {"DPTX", NULL, "DPTX_MCLK"},
1383 {"DPTX", NULL, "ETDM3_OUT_CG"},
1407 {"DPTX", NULL, "ETDM3_OUT_EN"},
1408 {"DPTX", NULL, "DPTX_EN"},
1667 {"DPTX", NULL, "DPTX_OUT_MUX"},
1669 {"ETDM_OUTPUT", NULL, "DPTX"},
2430 /* dptx configure */ in mtk_dai_hdmitx_dptx_hw_params()
2497 .name = "DPTX",
2500 .stream_name = "DPTX",
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| D | mt8188-mt6359.c | 153 SND_SOC_DAILINK_DEFS(dptx,
154 DAILINK_COMP_ARRAY(COMP_CPU("DPTX")),
1129 SND_SOC_DAILINK_REG(dptx),
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| /linux-6.14.4/Documentation/devicetree/bindings/display/rockchip/ |
| D | cdn-dp-rockchip.txt | 16 Required elements: "apb", "core", "dptx", "spdif"
|
| /linux-6.14.4/Documentation/devicetree/bindings/display/mediatek/ |
| D | mediatek,dp.yaml | 111 dptx@1c600000 {
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| /linux-6.14.4/Documentation/devicetree/bindings/phy/ |
| D | phy-cadence-torrent.yaml | 56 - description: Offset of the DPTX PHY configuration registers.
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| /linux-6.14.4/sound/soc/mediatek/mt8195/ |
| D | mt8195-dai-etdm.c | 1306 {"DPTX Playback", NULL, "DPTX_OUT_MUX"},
1308 {"ETDM_OUTPUT", NULL, "DPTX Playback"},
2369 /* dptx configure */ in mtk_dai_hdmitx_dptx_hw_params()
2412 /* enable dptx interface */ in mtk_dai_hdmitx_dptx_trigger()
2426 /* disable dptx interface */ in mtk_dai_hdmitx_dptx_trigger()
2521 .name = "DPTX",
2524 .stream_name = "DPTX Playback",
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| D | mt8195-mt6359.c | 814 DAILINK_COMP_ARRAY(COMP_CPU("DPTX")),
1279 dp_node = of_parse_phandle(dev->of_node, "mediatek,dptx-codec", 0); in mt8195_mt6359_legacy_probe()
1285 dev_dbg(dev, "No property 'dptx-codec'\n"); in mt8195_mt6359_legacy_probe()
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| /linux-6.14.4/drivers/clk/samsung/ |
| D | clk-exynosautov9.c | 502 /* DPTX */
672 /* DPTX */
829 /* DPTX */
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| D | clk-exynosautov920.c | 615 /* DPTX */
805 /* DPTX */
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| /linux-6.14.4/arch/arm64/boot/dts/mediatek/ |
| D | mt8390-genio-common.dtsi | 455 dptx_pins: dptx-pins {
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| D | mt8195-cherry.dtsi | 835 dptx_pin: dptx-default-pins {
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| /linux-6.14.4/drivers/gpu/drm/i915/display/ |
| D | intel_dp_link_training.c | 283 * The DPTX shall read the DPRX caps after LTTPR detection, so re-read in intel_dp_init_lttpr_and_dprx_caps()
812 * Prior to LT DPTX should set 128b/132b DP Channel coding and then set link rate in intel_dp_prepare_link_train()
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| /linux-6.14.4/drivers/thunderbolt/ |
| D | tb.c | 2684 * makes the DPTX request fail on graphics side. in tb_alloc_dp_bandwidth()
2739 tb_port_dbg(in, "DPTX disabled bandwidth allocation mode\n"); in tb_handle_dp_bandwidth_request()
2756 tb_port_dbg(in, "DPTX enabled bandwidth allocation mode, updating estimated bandwidth\n"); in tb_handle_dp_bandwidth_request()
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| /linux-6.14.4/drivers/phy/cadence/ |
| D | phy-cadence-torrent.c | 62 * register offsets from DPTX PHY register block base (i.e MHDP
350 void __iomem *base; /* DPTX registers base */
611 /* DPTX mmr access functions */
2219 dev_err(dev, "Failed to init DPTX PHY regmap\n"); in cdns_torrent_dp_regmap_init()
3036 /* DPTX registers */ in cdns_torrent_phy_probe()
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