1# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
2# Copyright (C) 2020 Texas Instruments Incorporated
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/net/ti,dp83822.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: TI DP83822 ethernet PHY
9
10maintainers:
11  - Andrew Davis <[email protected]>
12
13description: |
14  The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
15  provides all of the physical layer functions needed to transmit and receive
16  data over standard, twisted-pair cables or to connect to an external,
17  fiber-optic transceiver. Additionally, the DP83822 provides flexibility to
18  connect to a MAC through a standard MII, RMII, or RGMII interface
19
20  Specifications about the Ethernet PHY can be found at:
21    http://www.ti.com/lit/ds/symlink/dp83822i.pdf
22
23allOf:
24  - $ref: ethernet-phy.yaml#
25
26properties:
27  reg:
28    maxItems: 1
29
30  ti,link-loss-low:
31    type: boolean
32    description: |
33       DP83822 PHY in Fiber mode only.
34       Sets the DP83822 to detect a link drop condition when the signal goes
35       high.  If not set then link drop will occur when the signal goes low.
36       This property is only applicable if the fiber mode support is strapped
37       to on.
38
39  ti,fiber-mode:
40    type: boolean
41    description: |
42       DP83822 PHY only.
43       If present the DP83822 PHY is configured to operate in fiber mode
44       Fiber mode support can also be strapped. If the strap pin is not set
45       correctly or not set at all then this boolean can be used to enable it.
46       If the fiber mode is not strapped then signal detection for the PHY
47       is disabled.
48       In fiber mode, auto-negotiation is disabled and the PHY can only work in
49       100base-fx (full and half duplex) modes.
50
51  rx-internal-delay-ps:
52    description: |
53       DP83822 PHY only.
54       Setting this property to a non-zero number sets the RX internal delay
55       for the PHY.  The internal delay for the PHY is fixed to 3.5ns relative
56       to receive data.
57
58  tx-internal-delay-ps:
59    description: |
60       DP83822 PHY only.
61       Setting this property to a non-zero number sets the TX internal delay
62       for the PHY.  The internal delay for the PHY is fixed to 3.5ns relative
63       to transmit data.
64
65  ti,cfg-dac-minus-one-bp:
66    description: |
67       DP83826 PHY only.
68       Sets the voltage ratio (with respect to the nominal value)
69       of the logical level -1 for the MLT-3 encoded TX data.
70    enum: [5000, 5625, 6250, 6875, 7500, 8125, 8750, 9375, 10000,
71           10625, 11250, 11875, 12500, 13125, 13750, 14375, 15000]
72    default: 10000
73
74  ti,cfg-dac-plus-one-bp:
75    description: |
76       DP83826 PHY only.
77       Sets the voltage ratio (with respect to the nominal value)
78       of the logical level +1 for the MLT-3 encoded TX data.
79    enum: [5000, 5625, 6250, 6875, 7500, 8125, 8750, 9375, 10000,
80           10625, 11250, 11875, 12500, 13125, 13750, 14375, 15000]
81    default: 10000
82
83  ti,rmii-mode:
84    description: |
85       If present, select the RMII operation mode. Two modes are
86       available:
87         - RMII master, where the PHY outputs a 50MHz reference clock which can
88         be connected to the MAC.
89         - RMII slave, where the PHY expects a 50MHz reference clock input
90         shared with the MAC.
91       The RMII operation mode can also be configured by its straps.
92       If the strap pin is not set correctly or not set at all, then this can be
93       used to configure it.
94    $ref: /schemas/types.yaml#/definitions/string
95    enum:
96      - master
97      - slave
98
99  ti,gpio2-clk-out:
100    description: |
101       DP83822 PHY only.
102       The GPIO2 pin on the DP83822 can be configured as clock output. When
103       omitted, the PHY's default will be left as is.
104
105       - 'mac-if': In MII mode the clock frequency is 25-MHz, in RMII Mode the
106         clock frequency is 50-MHz and in RGMII Mode the clock frequency is
107         25-MHz.
108       - 'xi': XI clock(pass-through clock from XI pin).
109       - 'int-ref': Internal reference clock 25-MHz.
110       - 'rmii-master-mode-ref': RMII master mode reference clock 50-MHz. RMII
111         master mode reference clock is identical to MAC IF clock in RMII master
112         mode.
113       - 'free-running': Free running clock 125-MHz.
114       - 'recovered': Recovered clock is a 125-MHz recovered clock from a
115         connected link partner.
116    $ref: /schemas/types.yaml#/definitions/string
117    enum:
118      - mac-if
119      - xi
120      - int-ref
121      - rmii-master-mode-ref
122      - free-running
123      - recovered
124
125required:
126  - reg
127
128unevaluatedProperties: false
129
130examples:
131  - |
132    mdio0 {
133      #address-cells = <1>;
134      #size-cells = <0>;
135      ethphy0: ethernet-phy@0 {
136        reg = <0>;
137        rx-internal-delay-ps = <1>;
138        tx-internal-delay-ps = <1>;
139        ti,gpio2-clk-out = "xi";
140      };
141    };
142
143...
144