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/linux-6.14.4/Documentation/devicetree/bindings/dma/
Dlpc1850-dmamux.txt1 NXP LPC18xx/43xx DMA MUX (DMA request router)
4 - compatible: "nxp,lpc1850-dmamux"
5 - reg: Memory map for accessing module
6 - #dma-cells: Should be set to <3>.
7 * 1st cell contain the master dma request signal
8 * 2nd cell contain the mux value (0-3) for the peripheral
11 - dma-requests: Number of DMA requests for the mux
12 - dma-masters: phandle pointing to the DMA controller
14 The DMA controller node need to have the following poroperties:
15 - dma-requests: Number of DMA requests the controller can handle
[all …]
Dti-dma-crossbar.txt1 Texas Instruments DMA Crossbar (DMA request router)
4 - compatible: "ti,dra7-dma-crossbar" for DRA7xx DMA crossbar
5 "ti,am335x-edma-crossbar" for AM335x and AM437x
6 - reg: Memory map for accessing module
7 - #dma-cells: Should be set to match with the DMA controller's dma-cells
8 for ti,dra7-dma-crossbar and <3> for ti,am335x-edma-crossbar.
9 - dma-requests: Number of DMA requests the crossbar can receive
10 - dma-masters: phandle pointing to the DMA controller
12 The DMA controller node need to have the following poroperties:
13 - dma-requests: Number of DMA requests the controller can handle
[all …]
Dowl-dma.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/owl-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Actions Semi Owl SoCs DMA controller
10 The OWL DMA is a general-purpose direct memory access controller capable of
11 supporting 10 independent DMA channels for the Actions Semi S700 SoC and 12
12 independent DMA channels for the S500 and S900 SoC variants.
15 - Manivannan Sadhasivam <[email protected]>
18 - $ref: dma-controller.yaml#
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Drenesas,rzn1-dmamux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/renesas,rzn1-dmamux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/N1 DMA mux
10 - Miquel Raynal <[email protected]>
13 - $ref: dma-router.yaml#
17 const: renesas,rzn1-dmamux
21 description: DMA mux first register offset within the system control parent.
23 '#dma-cells':
[all …]
Dmediatek,uart-dma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/mediatek,uart-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Long Cheng <[email protected]>
13 The MediaTek UART APDMA controller provides DMA capabilities
17 - $ref: dma-controller.yaml#
22 - items:
23 - enum:
24 - mediatek,mt2712-uart-dma
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Ddma-router.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/dma-router.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DMA Router Common Properties
10 - Vinod Koul <[email protected]>
13 - $ref: dma-common.yaml#
16 DMA routers are transparent IP blocks used to route DMA request
17 lines from devices to the DMA controller. Some SoCs (like TI DRA7x)
18 have more peripherals integrated with DMA requests than what the DMA
[all …]
Dfsl,imx-dma.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/dma/fsl,imx-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Direct Memory Access (DMA) Controller for i.MX
10 - Animesh Agarwal <[email protected]>
13 - $ref: dma-controller.yaml#
18 - fsl,imx1-dma
19 - fsl,imx21-dma
20 - fsl,imx27-dma
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Dk3dma.txt1 * Hisilicon K3 DMA controller
3 See dma.txt first
6 - compatible: Must be one of
7 - "hisilicon,k3-dma-1.0"
8 - "hisilicon,hisi-pcm-asp-dma-1.0"
9 - reg: Should contain DMA registers location and length.
10 - interrupts: Should contain one interrupt shared by all channel
11 - #dma-cells: see dma.txt, should be 1, para number
12 - dma-channels: physical channels supported
13 - dma-requests: virtual channels supported, each virtual channel
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Drenesas,nbpfaxi.txt1 * Renesas "Type-AXI" NBPFAXI* DMA controllers
3 * DMA controller
7 - compatible: must be one of
17 - #dma-cells: must be 2: the first integer is a terminal number, to which this
26 - max-burst-mem-read: limit burst size for memory reads
29 - max-burst-mem-write: limit burst size for memory writes
32 If both max-burst-mem-read and max-burst-mem-write are set, DMA_MEM_TO_MEM
35 You can use dma-channels and dma-requests as described in dma.txt, although they
40 dma: dma-controller@48000000 {
51 #dma-cells = <2>;
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Dst_fdma.txt3 The FDMA is a general-purpose direct memory access controller capable of
4 supporting 16 independent DMA channels. It accepts up to 32 DMA requests.
10 - compatible : Should be one of
11 - st,stih407-fdma-mpe31-11, "st,slim-rproc";
12 - st,stih407-fdma-mpe31-12, "st,slim-rproc";
13 - st,stih407-fdma-mpe31-13, "st,slim-rproc";
14 - reg : Should contain an entry for each name in reg-names
15 - reg-names : Must contain "slimcore", "dmem", "peripherals", "imem" entries
16 - interrupts : Should contain one interrupt shared by all channels
17 - dma-channels : Number of channels supported by the controller
[all …]
Dsnps,dma-spear1340.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys Designware DMA Controller
10 - Viresh Kumar <[email protected]>
11 - Andy Shevchenko <[email protected]>
14 - $ref: dma-controller.yaml#
19 - const: snps,dma-spear1340
20 - items:
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/linux-6.14.4/Documentation/mm/
Dbalance.rst13 overhead of page reclaim. This may happen for opportunistic high-order
14 allocation requests that have order-0 fallback options. In such cases,
17 __GFP_IO allocation requests are made to prevent file system deadlocks.
19 In the absence of non sleepable allocation requests, it seems detrimental
24 That being said, the kernel should try to fulfill requests for direct
26 the dma pool, so as to keep the dma pool filled for dma requests (atomic
28 OTOH, if there is a lot of free dma pages, it is preferable to satisfy
29 regular memory requests by allocating one from the dma pool, instead
34 right ratio of dma and regular memory, it is quite possible that balancing
35 would not be done even when the dma zone was completely empty. 2.2 has
[all …]
/linux-6.14.4/drivers/dma/stm32/
Dstm32-dmamux.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Pierre-Yves Mordret <pierre-[email protected]>
8 * DMA Router driver for STM32 DMA MUX
10 * Based on TI DMA Crossbar driver
41 u32 dma_requests; /* Number of DMA requests connected to DMAMUX */
42 u32 dmamux_requests; /* Number of DMA requests routed toward DMAs */
44 DECLARE_BITMAP(dma_inuse, STM32_DMAMUX_MAX_DMA_REQUESTS); /* Used DMA channel */
48 u32 dma_reqs[]; /* Number of DMA Request per DMA masters.
49 * [0] holds number of DMA Masters.
70 /* Clear dma request */ in stm32_dmamux_free()
[all …]
/linux-6.14.4/drivers/dma/ti/
Ddma-crossbar.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
25 .compatible = "ti,dra7-dma-crossbar",
29 .compatible = "ti,am335x-edma-crossbar",
44 u32 dma_requests; /* number of DMA requests on eDMA */
60 writeb_relaxed(val, iomem + (63 - event % 4)); in ti_am335x_xbar_write()
71 map->mux_val, map->dma_line); in ti_am335x_xbar_free()
73 ti_am335x_xbar_write(xbar->iomem, map->dma_line, 0); in ti_am335x_xbar_free()
80 struct platform_device *pdev = of_find_device_by_node(ofdma->of_node); in ti_am335x_xbar_route_allocate()
84 if (dma_spec->args_count != 3) in ti_am335x_xbar_route_allocate()
[all …]
/linux-6.14.4/drivers/dma/
Dlpc18xx-dmamux.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * DMA Router driver for LPC18xx/43xx DMA MUX
7 * Based on TI DMA Crossbar driver by:
8 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
48 spin_lock_irqsave(&dmamux->lock, flags); in lpc18xx_dmamux_free()
49 mux->busy = false; in lpc18xx_dmamux_free()
50 spin_unlock_irqrestore(&dmamux->lock, flags); in lpc18xx_dmamux_free()
56 struct platform_device *pdev = of_find_device_by_node(ofdma->of_node); in lpc18xx_dmamux_reserve()
61 if (dma_spec->args_count != 3) { in lpc18xx_dmamux_reserve()
62 dev_err(&pdev->dev, "invalid number of dma mux args\n"); in lpc18xx_dmamux_reserve()
[all …]
/linux-6.14.4/Documentation/driver-api/rapidio/
Dmport_cdev.rst17 for user-space applications. Most of RapidIO operations are supported through
24 Using available set of ioctl commands user-space applications can perform
27 - Reads and writes from/to configuration registers of mport devices
29 - Reads and writes from/to configuration registers of remote RapidIO devices.
32 - Set RapidIO Destination ID for mport devices (RIO_MPORT_MAINT_HDID_SET)
33 - Set RapidIO Component Tag for mport devices (RIO_MPORT_MAINT_COMPTAG_SET)
34 - Query logical index of mport devices (RIO_MPORT_MAINT_PORT_IDX_GET)
35 - Query capabilities and RapidIO link configuration of mport devices
37 - Enable/Disable reporting of RapidIO doorbell events to user-space applications
39 - Enable/Disable reporting of RIO port-write events to user-space applications
[all …]
/linux-6.14.4/drivers/accel/qaic/
Dqaic.h1 /* SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
25 #define QAIC_NO_PARTITION -1
31 #define to_drm(qddev) (&(qddev)->drm)
32 #define to_accel_kdev(qddev) (to_drm(qddev)->accel->kdev) /* Return Linux device of accel node */
33 #define to_qaic_device(dev) (to_qaic_drm_device((dev))->qdev)
62 /* ID of this DMA bridge channel(DBC) */
84 * this requests that belong to same memory handle have same request ID
124 /* List of requests queued in MHI control device */
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/net/
Dsnps,dwc-qos-ethernet.txt13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
24 same order. See ../clock/clock-bindings.txt.
25 - clock-names: May contain any/all of the following depending on the IP
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/dma/stm32/
Dst,stm32-dma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 DMA Controller
10 The STM32 DMA is a general-purpose direct memory access controller capable of
11 supporting 8 independent DMA channels. Each channel can have up to 8 requests.
12 DMA clients connected to the STM32 DMA controller must use the format
13 described in the dma.txt file, using a four-cell specifier for each
14 channel: a phandle to the DMA controller plus the following four integer cells:
[all …]
Dst,stm32-mdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-mdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 MDMA is a general-purpose direct memory access controller capable of
11 supporting 64 independent DMA channels with 256 HW requests.
12 DMA clients connected to the STM32 MDMA controller must use the format
13 described in the dma.txt file, using a five-cell specifier for each channel:
21 3. A 32bit mask specifying the DMA channel configuration
22 -bit 0-1: Source increment mode
[all …]
/linux-6.14.4/Documentation/core-api/
Ddebugging-via-ohci1394.rst2 Using physical DMA provided by OHCI-1394 FireWire controllers for debugging
6 ------------
9 to the OHCI-1394 specification which defines the controller to be a PCI
10 bus master which uses DMA to offload data transfers from the CPU and has
11 a "Physical Response Unit" which executes specific requests by employing
12 PCI-Bus master DMA after applying filters defined by the OHCI-1394 driver.
14 Once properly configured, remote machines can send these requests to
15 ask the OHCI-1394 controller to perform read and write requests on
16 physical system memory and, for read requests, send the result of
28 hardware such as x86, x86-64 and PowerPC.
[all …]
Dswiotlb.rst1 .. SPDX-License-Identifier: GPL-2.0
4 DMA and swiotlb
7 swiotlb is a memory buffer allocator used by the Linux kernel DMA layer. It is
8 typically used when a device doing DMA can't directly access the target memory
10 the DMA layer calls swiotlb to allocate a temporary memory buffer that conforms
11 to the limitations. The DMA is done to/from this temporary memory buffer, and
17 the DMA layer of the DMA attributes of the devices they are managing, and use
18 the normal DMA map, unmap, and sync APIs when programming a device to do DMA.
19 These APIs use the device DMA attributes and kernel-wide settings to determine
20 if bounce buffering is necessary. If so, the DMA layer manages the allocation,
[all …]
/linux-6.14.4/Documentation/driver-api/mmc/
Dmmc-async-req.rst11 pre-fetch makes the cache overhead relatively significant. If the DMA
13 transfer, the DMA preparation overhead would not affect the MMC performance.
15 The intention of non-blocking (asynchronous) MMC requests is to minimize the
19 dma_unmap_sg are processing. Using non-blocking MMC requests makes it
26 The mmc_blk_issue_rw_rq() in the MMC block driver is made non-blocking.
33 platform. In power save mode, when clocks run on a lower frequency, the DMA
40 https://wiki.linaro.org/WorkingGroups/Kernel/Specs/StoragePerfMMC-async-req
48 truly non-blocking. If there is an ongoing async request it waits
56 There are two optional members in the mmc_host_ops -- pre_req() and
57 post_req() -- that the host driver may implement in order to move work
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/linux-6.14.4/Documentation/trace/
Dhisi-ptt.rst1 .. SPDX-License-Identifier: GPL-2.0
23 +--------------Core 0-------+
25 | | [Root Port]---[Endpoint]
26 | | [Root Port]---[Endpoint]
27 | | [Root Port]---[Endpoint]
28 Root Complex |------Core 1-------+
30 | | [Root Port]---[ Switch ]---[Endpoint]
31 | | [Root Port]---[Endpoint] `-[Endpoint]
32 | | [Root Port]---[Endpoint]
33 +---------------------------+
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/linux-6.14.4/Documentation/accel/qaic/
Daic100.rst1 .. SPDX-License-Identifier: GPL-2.0-only
10 The Qualcomm Cloud AI 100/AIC100 family of products (including SA9000P - part of
20 performance. AIC100 cards are multi-user capable and able to execute workloads
26 An AIC100 card consists of an AIC100 SoC, on-card DDR, and a set of misc
39 AIC100 implements MSI but does not implement MSI-X. AIC100 prefers 17 MSIs to
40 operate (1 for MHI, 16 for the DMA Bridge). Falling back to 1 MSI is possible in
44 hardware. AIC100 provides 3, 64-bit BARs.
48 * The second BAR is 2M in size, and exposes the DMA Bridge interface to the
54 From the host perspective, AIC100 has several key hardware components -
59 * DMA Bridge
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