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/aosp_15_r20/external/jsoup/src/test/resources/fuzztests/
HD64720.html.gz
/aosp_15_r20/external/rust/android-crates-io/crates/grpcio-sys/grpc/third_party/cares/cares/
DMakefile.netware148 DL = '
208 @echo $(DL)# DEF file for linking with $(LD)$(DL) > $@
209 @echo $(DL)# Do not edit this file - it is created by make!$(DL) >> $@
210 @echo $(DL)# All your changes will be lost!!$(DL) >> $@
211 @echo $(DL)#$(DL) >> $@
212 @echo $(DL)copyright "$(COPYR)"$(DL) >> $@
213 @echo $(DL)description "$(DESCR)"$(DL) >> $@
214 @echo $(DL)version $(VERSION)$(DL) >> $@
216 @echo $(DL)type $(NLMTYPE)$(DL) >> $@
219 @echo $(DL)stack $(STACK)$(DL) >> $@
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/aosp_15_r20/external/iproute2/devlink/
H A Ddevlink.c203 struct dl { struct
222 static int dl_argc(struct dl *dl) in dl_argc() argument
224 return dl->argc; in dl_argc()
227 static char *dl_argv(struct dl *dl) in dl_argv() argument
229 if (dl_argc(dl) == 0) in dl_argv()
231 return *dl->argv; in dl_argv()
234 static void dl_arg_inc(struct dl *dl) in dl_arg_inc() argument
236 if (dl_argc(dl) == 0) in dl_arg_inc()
238 dl->argc--; in dl_arg_inc()
239 dl->argv++; in dl_arg_inc()
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/aosp_15_r20/external/cronet/third_party/apache-portable-runtime/src/build/
H A DNWGNUtail.inc138 @echo $(DL)CC $<$(DL)
144 @echo $(DL)CCOPT_DEPENDS=$^$(DL)
147 @echo $(DL)GEN $@$(DL)
149 @echo $(DL)$(CFLAGS)$(DL)>> $@
152 @echo $(DL)$(XCFLAGS)$(DL)>> $@
155 @echo $(DL)$(foreach xincdir,$(strip $(subst ;,$(SPACE),$(XINCDIRS))),-I$(xincdir))$(DL)>> $@
158 @echo $(DL)$(foreach incdir,$(strip $(subst ;,$(SPACE),$(INCDIRS))),-I$(incdir))$(DL)>> $@
161 @echo $(DL)$(DEFINES)$(DL)>> $@
164 @echo $(DL)$(XDEFINES)$(DL)>> $@
169 @echo $(DL)CPP $<$(DL)
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/aosp_15_r20/external/jackson-databind/docs/javadoc/2.1/
H A Dserialized-form.html135 <DL>
139 <DL>
140 </DL>
141 </DL>
147 <DL>
152 <DL>
153 </DL>
154 </DL>
160 <DL>
163 <DL>
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/aosp_15_r20/external/rust/android-crates-io/crates/annotate-snippets/tests/
Ddl_from_snippet.rs2 use annotate_snippets::{display_list as dl, formatter::get_term_style, snippet};
16 let output = dl::DisplayList { in test_format_title()
17 body: vec![dl::DisplayLine::Raw(dl::DisplayRawLine::Annotation { in test_format_title()
18 annotation: dl::Annotation { in test_format_title()
19 annotation_type: dl::DisplayAnnotationType::Error, in test_format_title()
21 label: vec![dl::DisplayTextFragment { in test_format_title()
23 style: dl::DisplayTextStyle::Emphasis, in test_format_title()
33 assert_eq!(dl::DisplayList::from(input), output); in test_format_title()
53 let output = dl::DisplayList { in test_format_slice()
55 dl::DisplayLine::Source { in test_format_slice()
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/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp293 SDLoc dl(N); in PromoteIntRes_BITCAST() local
301 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp)); in PromoteIntRes_BITCAST()
305 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); in PromoteIntRes_BITCAST()
309 return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, GetPromotedFloat(InOp)); in PromoteIntRes_BITCAST()
318 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
333 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, in PromoteIntRes_BITCAST()
337 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp); in PromoteIntRes_BITCAST()
347 DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp)); in PromoteIntRes_BITCAST()
355 Res = DAG.getNode(ISD::SRL, dl, NOutVT, Res, in PromoteIntRes_BITCAST()
356 DAG.getConstant(ShiftAmt, dl, ShiftAmtTy)); in PromoteIntRes_BITCAST()
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H A DLegalizeDAG.cpp124 const SDLoc &dl);
126 const SDLoc &dl);
132 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, const SDLoc &dl,
137 bool &NeedInvert, const SDLoc &dl, SDValue &Chain,
162 const SDLoc &dl);
164 const SDLoc &dl, SDValue ChainIn);
170 void getSignAsIntValue(FloatSignAsInt &State, const SDLoc &DL,
172 SDValue modifySignAsInt(const FloatSignAsInt &State, const SDLoc &DL,
177 void PromoteLegalINT_TO_FP(SDNode *N, const SDLoc &dl,
179 void PromoteLegalFP_TO_INT(SDNode *N, const SDLoc &dl,
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H A DTargetLowering.cpp129 const SDLoc &dl, in makeLibCall() argument
168 CLI.setDebugLoc(dl) in makeLibCall()
286 const SDLoc &dl, const SDValue OldLHS, in softenSetCCOperands() argument
289 return softenSetCCOperands(DAG, VT, NewLHS, NewRHS, CCCode, dl, OldLHS, in softenSetCCOperands()
296 const SDLoc &dl, const SDValue OldLHS, in softenSetCCOperands() argument
402 auto Call = makeLibCall(DAG, LC1, RetVT, Ops, CallOptions, dl, Chain); in softenSetCCOperands()
404 NewRHS = DAG.getConstant(0, dl, RetVT); in softenSetCCOperands()
418 SDValue Tmp = DAG.getSetCC(dl, SetCCVT, NewLHS, NewRHS, CCCode); in softenSetCCOperands()
419 auto Call2 = makeLibCall(DAG, LC2, RetVT, Ops, CallOptions, dl, Chain); in softenSetCCOperands()
423 NewLHS = DAG.getSetCC(dl, SetCCVT, Call2.first, NewRHS, CCCode); in softenSetCCOperands()
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/aosp_15_r20/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp97 const SDLoc &dl);
99 const SDLoc &dl);
105 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, const SDLoc &dl,
110 bool &NeedInvert, const SDLoc &dl);
114 unsigned NumOps, bool isSigned, const SDLoc &dl);
132 const SDLoc &dl);
137 void getSignAsIntValue(FloatSignAsInt &State, const SDLoc &DL,
139 SDValue modifySignAsInt(const FloatSignAsInt &State, const SDLoc &DL,
144 const SDLoc &dl);
146 const SDLoc &dl);
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H A DLegalizeIntegerTypes.cpp255 SDLoc dl(N); in PromoteIntRes_BITCAST() local
263 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp)); in PromoteIntRes_BITCAST()
267 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); in PromoteIntRes_BITCAST()
271 return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, PromotedOp); in PromoteIntRes_BITCAST()
280 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
294 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, in PromoteIntRes_BITCAST()
298 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp); in PromoteIntRes_BITCAST()
305 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp)); in PromoteIntRes_BITCAST()
308 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
316 SDLoc dl(N); in PromoteIntRes_BSWAP() local
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H A DTargetLowering.cpp119 const SDLoc &dl, bool doesNotReturn, in makeLibCall() argument
141 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode()) in makeLibCall()
153 const SDLoc &dl) const { in softenSetCCOperands()
256 dl).first; in softenSetCCOperands()
257 NewRHS = DAG.getConstant(0, dl, RetVT); in softenSetCCOperands()
265 ISD::SETCC, dl, in softenSetCCOperands()
269 dl).first; in softenSetCCOperands()
271 ISD::SETCC, dl, in softenSetCCOperands()
274 NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS); in softenSetCCOperands()
342 SDLoc dl(Op); in ShrinkDemandedConstant() local
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/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp498 const SDLoc &dl, SelectionDAG &DAG) const { in getInt() argument
500 IntOps.push_back(DAG.getConstant(IntId, dl, MVT::i32)); in getInt()
502 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, ResTy, IntOps); in getInt()
547 HexagonTargetLowering::opJoin(const VectorPair &Ops, const SDLoc &dl, in opJoin() argument
549 return DAG.getNode(ISD::CONCAT_VECTORS, dl, typeJoin(ty(Ops)), in opJoin()
554 HexagonTargetLowering::opSplit(SDValue Vec, const SDLoc &dl, in opSplit() argument
559 return DAG.SplitVector(Vec, dl, Tys.first, Tys.second); in opSplit()
612 DebugLoc DL = MI.getDebugLoc(); in AdjustHvxInstrPostInstrSelection() local
621 BuildMI(MB, At, DL, TII.get(Hexagon::A2_tfrsi), SplatV) in AdjustHvxInstrPostInstrSelection()
624 BuildMI(MB, At, DL, TII.get(Hexagon::V6_lvsplatb), OutV) in AdjustHvxInstrPostInstrSelection()
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/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp147 const SDLoc &dl, in makeLibCall() argument
186 CLI.setDebugLoc(dl) in makeLibCall()
292 const SDLoc &dl, const SDValue OldLHS, in softenSetCCOperands() argument
295 return softenSetCCOperands(DAG, VT, NewLHS, NewRHS, CCCode, dl, OldLHS, in softenSetCCOperands()
302 const SDLoc &dl, const SDValue OldLHS, in softenSetCCOperands() argument
408 auto Call = makeLibCall(DAG, LC1, RetVT, Ops, CallOptions, dl, Chain); in softenSetCCOperands()
410 NewRHS = DAG.getConstant(0, dl, RetVT); in softenSetCCOperands()
424 SDValue Tmp = DAG.getSetCC(dl, SetCCVT, NewLHS, NewRHS, CCCode); in softenSetCCOperands()
425 auto Call2 = makeLibCall(DAG, LC2, RetVT, Ops, CallOptions, dl, Chain); in softenSetCCOperands()
429 NewLHS = DAG.getSetCC(dl, SetCCVT, Call2.first, NewRHS, CCCode); in softenSetCCOperands()
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H A DLegalizeIntegerTypes.cpp390 SDLoc dl(N); in PromoteIntRes_BITCAST() local
398 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp)); in PromoteIntRes_BITCAST()
402 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); in PromoteIntRes_BITCAST()
405 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftPromotedHalf(InOp)); in PromoteIntRes_BITCAST()
409 return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, GetPromotedFloat(InOp)); in PromoteIntRes_BITCAST()
418 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
435 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, in PromoteIntRes_BITCAST()
439 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp); in PromoteIntRes_BITCAST()
449 DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp)); in PromoteIntRes_BITCAST()
456 Res = DAG.getNode(ISD::SRL, dl, NOutVT, Res, in PromoteIntRes_BITCAST()
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H A DLegalizeDAG.cpp124 const SDLoc &dl);
126 const SDLoc &dl);
132 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, const SDLoc &dl,
160 const SDLoc &dl);
162 const SDLoc &dl, SDValue ChainIn);
168 void getSignAsIntValue(FloatSignAsInt &State, const SDLoc &DL,
170 SDValue modifySignAsInt(const FloatSignAsInt &State, const SDLoc &DL,
176 void PromoteLegalINT_TO_FP(SDNode *N, const SDLoc &dl,
178 void PromoteLegalFP_TO_INT(SDNode *N, const SDLoc &dl,
180 SDValue PromoteLegalFP_TO_INT_SAT(SDNode *Node, const SDLoc &dl);
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/aosp_15_r20/tools/test/connectivity/acts/framework/acts/controllers/cellular_lib/
DLteSimulation.py57 """ DL/UL Duplex mode """
63 """DL/UL Modulation order."""
76 # Bandwidth [MHz] to minimum number of DL RBs that can be assigned to a UE
180 # Dictionary of lower DL channel number bound for each band.
232 5: {'DL': 3.82, 'UL': 2.63},
233 10: {'DL': 11.31,'UL': 9.03},
234 15: {'DL': 16.9, 'UL': 20.62},
235 20: {'DL': 22.88, 'UL': 28.43}
238 5: {'DL': 6.13, 'UL': 4.08},
239 10: {'DL': 18.36, 'UL': 9.69},
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/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp209 const SDLoc &dl, SelectionDAG &DAG) const { in getInt() argument
211 IntOps.push_back(DAG.getConstant(IntId, dl, MVT::i32)); in getInt()
214 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, ResTy, IntOps); in getInt()
259 HexagonTargetLowering::opJoin(const VectorPair &Ops, const SDLoc &dl, in opJoin() argument
261 return DAG.getNode(ISD::CONCAT_VECTORS, dl, typeJoin(ty(Ops)), in opJoin()
266 HexagonTargetLowering::opSplit(SDValue Vec, const SDLoc &dl, in opSplit() argument
271 return DAG.SplitVector(Vec, dl, Tys.first, Tys.second); in opSplit()
297 const SDLoc &dl(ElemIdx); in convertToByteIndex() local
298 return DAG.getNode(ISD::SHL, dl, MVT::i32, in convertToByteIndex()
299 {ElemIdx, DAG.getConstant(L, dl, MVT::i32)}); in convertToByteIndex()
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/aosp_15_r20/external/autotest/server/cros/cellular/simulation_utils/
H A DLteSimulation.py40 """ DL/UL Duplex mode """
46 """DL/UL Modulation order."""
109 # Bandwidth [MHz] to minimum number of DL RBs that can be assigned to a UE
186 5: {'DL': 3.82, 'UL': 2.63},
187 10: {'DL': 11.31,'UL': 9.03},
188 15: {'DL': 16.9, 'UL': 20.62},
189 20: {'DL': 22.88, 'UL': 28.43}
192 5: {'DL': 6.13, 'UL': 4.08},
193 10: {'DL': 18.36, 'UL': 9.69},
194 15: {'DL': 28.62, 'UL': 14.21},
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/aosp_15_r20/external/jackson-databind/docs/javadoc/2.0/com/fasterxml/jackson/databind/
H A DJsonNode.html99 <DL>
101 </DL>
102 <DL>
104 </DL>
106 <DL>
107 …ckson/databind/JsonNode.html" title="class in com.fasterxml.jackson.databind">JsonNode</A>&gt;</DL>
819 <DL>
820 <DL>
821 </DL>
822 </DL>
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/aosp_15_r20/external/jackson-core/docs/javadoc/2.1/
H A Dserialized-form.html131 <DL>
135 <DD><DL>
137 </DL>
138 </DL>
151 <DL>
157 <DL>
158 </DL>
159 </DL>
187 <DL>
192 <DD><DL>
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/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp201 const SDLoc &DL, SelectionDAG &DAG) const { in LowerReturn() argument
203 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG); in LowerReturn()
204 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG); in LowerReturn()
212 const SDLoc &DL, SelectionDAG &DAG) const { in LowerReturn_32() argument
244 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerReturn_32()
246 DAG.getConstant(0, DL, getVectorIdxTy(DAG.getDataLayout()))); in LowerReturn_32()
247 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerReturn_32()
249 DAG.getConstant(1, DL, getVectorIdxTy(DAG.getDataLayout()))); in LowerReturn_32()
251 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part0, Flag); in LowerReturn_32()
255 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part1, in LowerReturn_32()
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/aosp_15_r20/external/jackson-databind/docs/javadoc/2.1/com/fasterxml/jackson/databind/
H A DJsonNode.html99 <DL>
101 </DL>
102 <DL>
104 </DL>
106 <DL>
107 …ckson/databind/JsonNode.html" title="class in com.fasterxml.jackson.databind">JsonNode</A>&gt;</DL>
837 <DL>
838 <DL>
839 </DL>
840 </DL>
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/aosp_15_r20/external/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp199 const SDLoc &DL, SelectionDAG &DAG) const { in LowerReturn() argument
201 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG); in LowerReturn()
202 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG); in LowerReturn()
210 const SDLoc &DL, SelectionDAG &DAG) const { in LowerReturn_32() argument
242 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerReturn_32()
244 DAG.getConstant(0, DL, getVectorIdxTy(DAG.getDataLayout()))); in LowerReturn_32()
245 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerReturn_32()
247 DAG.getConstant(1, DL, getVectorIdxTy(DAG.getDataLayout()))); in LowerReturn_32()
249 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part0, Flag); in LowerReturn_32()
253 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part1, in LowerReturn_32()
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/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.cpp24 static SDValue createMemMemNode(SelectionDAG &DAG, const SDLoc &DL, unsigned Op, in createMemMemNode() argument
34 return DAG.getNode(Op, DL, VTs, Ops); in createMemMemNode()
41 static SDValue emitMemMemImm(SelectionDAG &DAG, const SDLoc &DL, unsigned Op, in emitMemMemImm() argument
46 SDValue LenAdj = DAG.getConstant(Size - Adj, DL, Dst.getValueType()); in emitMemMemImm()
47 return createMemMemNode(DAG, DL, Op, Chain, Dst, Src, LenAdj, Byte); in emitMemMemImm()
50 static SDValue emitMemMemReg(SelectionDAG &DAG, const SDLoc &DL, unsigned Op, in emitMemMemReg() argument
54 SDValue LenAdj = DAG.getNode(ISD::ADD, DL, MVT::i64, in emitMemMemReg()
55 DAG.getZExtOrTrunc(Size, DL, MVT::i64), in emitMemMemReg()
56 DAG.getConstant(0 - Adj, DL, MVT::i64)); in emitMemMemReg()
57 return createMemMemNode(DAG, DL, Op, Chain, Dst, Src, LenAdj, Byte); in emitMemMemReg()
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