/aosp_15_r20/external/coreboot/src/soc/intel/xeon_sp/ebg/include/soc/ |
H A D | gpio_soc_defs.h | 88 * Order 45-52 belongs to fields which are not described in EDS but 139 #define GPP_D3 91 // Not described in EDS 140 #define GPP_D4 92 // Not described in EDS 141 #define GPP_D5 93 // Not described in EDS 185 #define GPP_E20 132 // Not described in EDS 186 #define GPP_E21 133 // Not described in EDS 187 #define GPP_E22 134 // Not described in EDS 188 #define GPP_E23 135 // Not described in EDS 196 #define GPPC_H2 138 // Not described in EDS 197 #define GPPC_H3 139 // Not described in EDS [all …]
|
/aosp_15_r20/external/python/apitools/apitools/base/protorpclite/ |
D | descriptor_test.py | 50 described = descriptor.describe_enum_value(MyEnum.MY_NAME) 51 described.check_initialized() 52 self.assertEquals(expected, described) 64 described = descriptor.describe_enum(EmptyEnum) 65 described.check_initialized() 66 self.assertEquals(expected, described) 77 described = descriptor.describe_enum(MyScope.NestedEnum) 78 described.check_initialized() 79 self.assertEquals(expected, described) 106 described = descriptor.describe_enum(EnumWithItems) [all …]
|
/aosp_15_r20/external/coreboot/util/inteltool/gpio_names/ |
H A D | emmitsburg.h | 150 "GPP_D3", "n/a", // Not described in EDS, add here to take space 151 "GPP_D4", "n/a", // Not described in EDS, add here to take space 152 "GPP_D5", "n/a", // Not described in EDS, add here to take space 258 "GPPC_H2", "n/a", "n/a", // Not described in EDS, add here to take space 259 "GPPC_H3", "n/a", "n/a", // Not described in EDS, add here to take space 260 "GPPC_H4", "n/a", "n/a", // Not described in EDS, add here to take space 261 "GPPC_H5", "n/a", "n/a", // Not described in EDS, add here to take space 264 "GPPC_H8", "n/a", "n/a", // Not described in EDS, add here to take space 265 "GPPC_H9", "n/a", "n/a", // Not described in EDS, add here to take space 266 "GPPC_H10", "n/a", "n/a", // Not described in EDS, add here to take space [all …]
|
/aosp_15_r20/external/coreboot/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/ |
H A D | GoldmontMsr.h | 44 Described by the type MSR_GOLDMONT_FEATURE_CONTROL_REGISTER. 46 Described by the type MSR_GOLDMONT_FEATURE_CONTROL_REGISTER. 112 Described by the type MSR_GOLDMONT_PLATFORM_INFO_REGISTER. 114 Described by the type MSR_GOLDMONT_PLATFORM_INFO_REGISTER. 187 Described by the type 190 Described by the type 254 Described by the type MSR_GOLDMONT_SMM_MCA_CAP_REGISTER. 256 Described by the type MSR_GOLDMONT_SMM_MCA_CAP_REGISTER. 306 Described by the type MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER. 308 Described by the type MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER. [all …]
|
H A D | XeonDMsr.h | 45 Described by the type MSR_XEON_D_PPIN_CTL_REGISTER. 47 Described by the type MSR_XEON_D_PPIN_CTL_REGISTER. 114 Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER. 116 Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER. 184 Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER. 186 Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER. 276 Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER. 278 Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER. 355 Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER. 357 Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER. [all …]
|
H A D | SilvermontMsr.h | 48 Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER. 50 Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER. 95 Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER. 97 Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER. 137 Described by the type MSR_SILVERMONT_SMI_COUNT_REGISTER. 139 Described by the type MSR_SILVERMONT_SMI_COUNT_REGISTER. 182 Described by the type 185 Described by the type 312 Described by the type MSR_SILVERMONT_FSB_FREQ_REGISTER. 314 Described by the type MSR_SILVERMONT_FSB_FREQ_REGISTER. [all …]
|
H A D | SkylakeMsr.h | 50 Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER. 52 Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER. 130 Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER. 132 Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER. 251 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER. 253 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER. 363 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER. 365 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER. 476 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER. 478 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER. [all …]
|
H A D | HaswellMsr.h | 46 Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER. 48 Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER. 127 described inTable 2-2 and the fields below. 131 Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER. 133 Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER. 230 described inTable 2-2 and the fields below. 234 Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER. 236 Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER. 339 Described by the type MSR_HASWELL_LBR_SELECT_REGISTER. 341 Described by the type MSR_HASWELL_LBR_SELECT_REGISTER. [all …]
|
/aosp_15_r20/external/coreboot/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Register/Intel/Msr/ |
H A D | GoldmontMsr.h | 44 Described by the type MSR_GOLDMONT_FEATURE_CONTROL_REGISTER. 46 Described by the type MSR_GOLDMONT_FEATURE_CONTROL_REGISTER. 111 Described by the type MSR_GOLDMONT_PLATFORM_INFO_REGISTER. 113 Described by the type MSR_GOLDMONT_PLATFORM_INFO_REGISTER. 185 Described by the type 188 Described by the type 251 Described by the type MSR_GOLDMONT_SMM_MCA_CAP_REGISTER. 253 Described by the type MSR_GOLDMONT_SMM_MCA_CAP_REGISTER. 302 Described by the type MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER. 304 Described by the type MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER. [all …]
|
H A D | XeonDMsr.h | 45 Described by the type MSR_XEON_D_PPIN_CTL_REGISTER. 47 Described by the type MSR_XEON_D_PPIN_CTL_REGISTER. 112 Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER. 114 Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER. 181 Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER. 183 Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER. 272 Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER. 274 Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER. 350 Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER. 352 Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER. [all …]
|
H A D | SilvermontMsr.h | 48 Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER. 50 Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER. 94 Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER. 96 Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER. 135 Described by the type MSR_SILVERMONT_SMI_COUNT_REGISTER. 137 Described by the type MSR_SILVERMONT_SMI_COUNT_REGISTER. 179 Described by the type 182 Described by the type 306 Described by the type MSR_SILVERMONT_FSB_FREQ_REGISTER. 308 Described by the type MSR_SILVERMONT_FSB_FREQ_REGISTER. [all …]
|
H A D | SkylakeMsr.h | 50 Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER. 52 Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER. 128 Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER. 130 Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER. 248 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER. 250 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER. 359 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER. 361 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER. 471 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER. 473 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER. [all …]
|
H A D | HaswellMsr.h | 46 Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER. 48 Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER. 126 described inTable 2-2 and the fields below. 130 Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER. 132 Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER. 228 described inTable 2-2 and the fields below. 232 Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER. 234 Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER. 336 Described by the type MSR_HASWELL_LBR_SELECT_REGISTER. 338 Described by the type MSR_HASWELL_LBR_SELECT_REGISTER. [all …]
|
/aosp_15_r20/external/coreboot/src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Intel/Msr/ |
H A D | GoldmontMsr.h | 44 Described by the type MSR_GOLDMONT_FEATURE_CONTROL_REGISTER. 46 Described by the type MSR_GOLDMONT_FEATURE_CONTROL_REGISTER. 112 Described by the type MSR_GOLDMONT_PLATFORM_INFO_REGISTER. 114 Described by the type MSR_GOLDMONT_PLATFORM_INFO_REGISTER. 187 Described by the type 190 Described by the type 254 Described by the type MSR_GOLDMONT_SMM_MCA_CAP_REGISTER. 256 Described by the type MSR_GOLDMONT_SMM_MCA_CAP_REGISTER. 306 Described by the type MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER. 308 Described by the type MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER. [all …]
|
H A D | XeonDMsr.h | 45 Described by the type MSR_XEON_D_PPIN_CTL_REGISTER. 47 Described by the type MSR_XEON_D_PPIN_CTL_REGISTER. 114 Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER. 116 Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER. 184 Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER. 186 Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER. 276 Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER. 278 Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER. 355 Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER. 357 Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER. [all …]
|
H A D | SilvermontMsr.h | 48 Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER. 50 Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER. 95 Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER. 97 Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER. 137 Described by the type MSR_SILVERMONT_SMI_COUNT_REGISTER. 139 Described by the type MSR_SILVERMONT_SMI_COUNT_REGISTER. 182 Described by the type 185 Described by the type 312 Described by the type MSR_SILVERMONT_FSB_FREQ_REGISTER. 314 Described by the type MSR_SILVERMONT_FSB_FREQ_REGISTER. [all …]
|
H A D | SkylakeMsr.h | 50 Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER. 52 Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER. 130 Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER. 132 Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER. 251 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER. 253 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER. 363 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER. 365 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER. 476 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER. 478 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER. [all …]
|
H A D | HaswellMsr.h | 46 Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER. 48 Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER. 127 described inTable 2-2 and the fields below. 131 Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER. 133 Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER. 230 described inTable 2-2 and the fields below. 234 Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER. 236 Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER. 339 Described by the type MSR_HASWELL_LBR_SELECT_REGISTER. 341 Described by the type MSR_HASWELL_LBR_SELECT_REGISTER. [all …]
|
H A D | XeonPhiMsr.h | 45 Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER. 47 Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER. 88 Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER. 90 Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER. 169 Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER. 171 Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER. 236 Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER. 238 Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER. 312 Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER. 314 Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER. [all …]
|
/aosp_15_r20/external/coreboot/src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Intel/ |
H A D | ArchitecturalMsr.h | 106 Described by the type MSR_IA32_PLATFORM_ID_REGISTER. 108 Described by the type MSR_IA32_PLATFORM_ID_REGISTER. 159 Described by the type MSR_IA32_APIC_BASE_REGISTER. 161 Described by the type MSR_IA32_APIC_BASE_REGISTER. 219 Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER. 221 Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER. 371 Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER. 373 Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER. 449 Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER. 451 Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER. [all …]
|
/aosp_15_r20/external/coreboot/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Register/Intel/ |
H A D | ArchitecturalMsr.h | 102 Described by the type MSR_IA32_PLATFORM_ID_REGISTER. 104 Described by the type MSR_IA32_PLATFORM_ID_REGISTER. 154 Described by the type MSR_IA32_APIC_BASE_REGISTER. 156 Described by the type MSR_IA32_APIC_BASE_REGISTER. 213 Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER. 215 Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER. 362 Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER. 364 Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER. 438 Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER. 440 Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER. [all …]
|
/aosp_15_r20/external/coreboot/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/ |
H A D | ArchitecturalMsr.h | 106 Described by the type MSR_IA32_PLATFORM_ID_REGISTER. 108 Described by the type MSR_IA32_PLATFORM_ID_REGISTER. 159 Described by the type MSR_IA32_APIC_BASE_REGISTER. 161 Described by the type MSR_IA32_APIC_BASE_REGISTER. 219 Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER. 221 Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER. 371 Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER. 373 Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER. 449 Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER. 451 Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER. [all …]
|
/aosp_15_r20/external/python/google-api-python-client/docs/dyn/ |
D | privateca_v1beta1.projects.locations.certificateAuthorities.certificates.html | 144 …quot;: { # KeyUsage.KeyUsageOptions corresponds to the key usage values described in https://tools… 156 …uot;: True or False, # Corresponds to OID 1.3.6.1.5.5.7.3.2. Officially described as "TLS WWW… 157 …uot;: True or False, # Corresponds to OID 1.3.6.1.5.5.7.3.3. Officially described as "Signing… 158 …uot;: True or False, # Corresponds to OID 1.3.6.1.5.5.7.3.4. Officially described as "Email p… 159 …uot;: True or False, # Corresponds to OID 1.3.6.1.5.5.7.3.9. Officially described as "Signing… 160 …uot;: True or False, # Corresponds to OID 1.3.6.1.5.5.7.3.1. Officially described as "TLS WWW… 161 …uot;: True or False, # Corresponds to OID 1.3.6.1.5.5.7.3.8. Officially described as "Binding… 179 …ocations to obtain CRL information, i.e. the DistributionPoint.fullName described by https://tools… 183 …cified in a request, the padding and encoding can be any of the options described by the respectiv… 233 …cified in a request, the padding and encoding can be any of the options described by the respectiv… [all …]
|
D | privateca_v1.projects.locations.caPools.certificates.html | 124 …ocations to obtain CRL information, i.e. the DistributionPoint.fullName described by https://tools… 195 …quot;: { # KeyUsage.KeyUsageOptions corresponds to the key usage values described in https://tools… 207 …uot;: True or False, # Corresponds to OID 1.3.6.1.5.5.7.3.2. Officially described as "TLS WWW… 208 …uot;: True or False, # Corresponds to OID 1.3.6.1.5.5.7.3.3. Officially described as "Signing… 209 …uot;: True or False, # Corresponds to OID 1.3.6.1.5.5.7.3.4. Officially described as "Email p… 210 …uot;: True or False, # Corresponds to OID 1.3.6.1.5.5.7.3.9. Officially described as "Signing… 211 …uot;: True or False, # Corresponds to OID 1.3.6.1.5.5.7.3.1. Officially described as "TLS WWW… 212 …uot;: True or False, # Corresponds to OID 1.3.6.1.5.5.7.3.8. Officially described as "Binding… 294 …quot;: { # KeyUsage.KeyUsageOptions corresponds to the key usage values described in https://tools… 306 …uot;: True or False, # Corresponds to OID 1.3.6.1.5.5.7.3.2. Officially described as "TLS WWW… [all …]
|
/aosp_15_r20/external/ltp/testcases/open_posix_testsuite/conformance/definitions/pthread_h/ |
H A D | assertions.xml | 34 Type 'pthread_attr_t' shall be defined as described in sys/types.h 35 Type 'pthread_barrier_t' shall be defined as described in sys/types.h 36 Type 'pthread_barrierattr_t' shall be defined as described in sys/types.h 37 Type 'pthread_cond_t' shall be defined as described in sys/types.h 38 Type 'pthread_condattr_t' shall be defined as described in sys/types.h 39 Type 'pthread_key_t' shall be defined as described in sys/types.h 40 Type 'pthread_mutex_t' shall be defined as described in sys/types.h 41 Type 'pthread_mutexattr_t' shall be defined as described in sys/types.h 42 Type 'pthread_once_t' shall be defined as described in sys/types.h 43 Type 'pthread_rwlock_t' shall be defined as described in sys/types.h [all …]
|