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/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
H A DIntrinsicsHexagon.td71 def int_hexagon_circ_ldd :
76 def int_hexagon_circ_ldw :
81 def int_hexagon_circ_ldh :
86 def int_hexagon_circ_lduh :
91 def int_hexagon_circ_ldb :
96 def int_hexagon_circ_ldub :
102 def int_hexagon_circ_std :
107 def int_hexagon_circ_stw :
112 def int_hexagon_circ_sth :
117 def int_hexagon_circ_sthhi :
[all …]
H A DIntrinsicsAArch64.td15 def int_aarch64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>;
16 def int_aarch64_ldaxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>;
17 def int_aarch64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>;
18 def int_aarch64_stlxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>;
20 def int_aarch64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>;
21 def int_aarch64_ldaxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>;
22 def int_aarch64_stxp : Intrinsic<[llvm_i32_ty],
24 def int_aarch64_stlxp : Intrinsic<[llvm_i32_ty],
27 def int_aarch64_clrex : Intrinsic<[]>;
29 def int_aarch64_sdiv : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
[all …]
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r522817/include/llvm/IR/
DIntrinsicsHexagonDep.td1063 def int_hexagon_A2_abs :
1066 def int_hexagon_A2_absp :
1069 def int_hexagon_A2_abssat :
1072 def int_hexagon_A2_add :
1075 def int_hexagon_A2_addh_h16_hh :
1078 def int_hexagon_A2_addh_h16_hl :
1081 def int_hexagon_A2_addh_h16_lh :
1084 def int_hexagon_A2_addh_h16_ll :
1087 def int_hexagon_A2_addh_h16_sat_hh :
1090 def int_hexagon_A2_addh_h16_sat_hl :
[all …]
DIntrinsicsAArch64.td15 def int_aarch64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty],
17 def int_aarch64_ldaxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty],
19 def int_aarch64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty],
21 def int_aarch64_stlxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty],
24 def int_aarch64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty],
26 def int_aarch64_ldaxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty],
28 def int_aarch64_stxp : Intrinsic<[llvm_i32_ty],
31 def int_aarch64_stlxp : Intrinsic<[llvm_i32_ty],
35 def int_aarch64_clrex : Intrinsic<[]>;
37 def int_aarch64_sdiv : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
[all …]
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r536225/include/llvm/IR/
DIntrinsicsHexagonDep.td1063 def int_hexagon_A2_abs :
1066 def int_hexagon_A2_absp :
1069 def int_hexagon_A2_abssat :
1072 def int_hexagon_A2_add :
1075 def int_hexagon_A2_addh_h16_hh :
1078 def int_hexagon_A2_addh_h16_hl :
1081 def int_hexagon_A2_addh_h16_lh :
1084 def int_hexagon_A2_addh_h16_ll :
1087 def int_hexagon_A2_addh_h16_sat_hh :
1090 def int_hexagon_A2_addh_h16_sat_hl :
[all …]
DIntrinsicsAArch64.td15 def int_aarch64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty],
17 def int_aarch64_ldaxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty],
19 def int_aarch64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty],
21 def int_aarch64_stlxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty],
24 def int_aarch64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty],
26 def int_aarch64_ldaxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty],
28 def int_aarch64_stxp : Intrinsic<[llvm_i32_ty],
31 def int_aarch64_stlxp : Intrinsic<[llvm_i32_ty],
35 def int_aarch64_clrex : Intrinsic<[]>;
37 def int_aarch64_sdiv : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
[all …]
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567b/include/llvm/IR/
DIntrinsicsHexagonDep.td1063 def int_hexagon_A2_abs :
1066 def int_hexagon_A2_absp :
1069 def int_hexagon_A2_abssat :
1072 def int_hexagon_A2_add :
1075 def int_hexagon_A2_addh_h16_hh :
1078 def int_hexagon_A2_addh_h16_hl :
1081 def int_hexagon_A2_addh_h16_lh :
1084 def int_hexagon_A2_addh_h16_ll :
1087 def int_hexagon_A2_addh_h16_sat_hh :
1090 def int_hexagon_A2_addh_h16_sat_hl :
[all …]
DIntrinsicsAArch64.td15 def int_aarch64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty],
17 def int_aarch64_ldaxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty],
19 def int_aarch64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty],
21 def int_aarch64_stlxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty],
24 def int_aarch64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty],
26 def int_aarch64_ldaxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty],
28 def int_aarch64_stxp : Intrinsic<[llvm_i32_ty],
31 def int_aarch64_stlxp : Intrinsic<[llvm_i32_ty],
35 def int_aarch64_clrex : Intrinsic<[]>;
37 def int_aarch64_sdiv : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/include/llvm/IR/
H A DIntrinsicsHexagonDep.td1063 def int_hexagon_A2_abs :
1066 def int_hexagon_A2_absp :
1069 def int_hexagon_A2_abssat :
1072 def int_hexagon_A2_add :
1075 def int_hexagon_A2_addh_h16_hh :
1078 def int_hexagon_A2_addh_h16_hl :
1081 def int_hexagon_A2_addh_h16_lh :
1084 def int_hexagon_A2_addh_h16_ll :
1087 def int_hexagon_A2_addh_h16_sat_hh :
1090 def int_hexagon_A2_addh_h16_sat_hl :
[all …]
H A DIntrinsicsAArch64.td15 def int_aarch64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty],
17 def int_aarch64_ldaxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty],
19 def int_aarch64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty],
21 def int_aarch64_stlxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty],
24 def int_aarch64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty],
26 def int_aarch64_ldaxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty],
28 def int_aarch64_stxp : Intrinsic<[llvm_i32_ty],
31 def int_aarch64_stlxp : Intrinsic<[llvm_i32_ty],
35 def int_aarch64_clrex : Intrinsic<[]>;
37 def int_aarch64_sdiv : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
[all …]
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567/include/llvm/IR/
DIntrinsicsHexagonDep.td1063 def int_hexagon_A2_abs :
1066 def int_hexagon_A2_absp :
1069 def int_hexagon_A2_abssat :
1072 def int_hexagon_A2_add :
1075 def int_hexagon_A2_addh_h16_hh :
1078 def int_hexagon_A2_addh_h16_hl :
1081 def int_hexagon_A2_addh_h16_lh :
1084 def int_hexagon_A2_addh_h16_ll :
1087 def int_hexagon_A2_addh_h16_sat_hh :
1090 def int_hexagon_A2_addh_h16_sat_hl :
[all …]
DIntrinsicsAArch64.td15 def int_aarch64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty],
17 def int_aarch64_ldaxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty],
19 def int_aarch64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty],
21 def int_aarch64_stlxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty],
24 def int_aarch64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty],
26 def int_aarch64_ldaxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty],
28 def int_aarch64_stxp : Intrinsic<[llvm_i32_ty],
31 def int_aarch64_stlxp : Intrinsic<[llvm_i32_ty],
35 def int_aarch64_clrex : Intrinsic<[]>;
37 def int_aarch64_sdiv : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
[all …]
/aosp_15_r20/external/llvm/lib/Target/X86/
H A DX86Schedule.td17 def ReadAfterLd : SchedRead;
21 def WriteRMW : SchedWrite;
35 def Ld : SchedWrite;
37 def NAME : X86FoldableSchedWrite {
45 def WriteIMulH : SchedWrite; // Integer multiplication, high part.
47 def WriteLEA : SchedWrite; // LEA instructions can't fold loads.
53 def WriteLoad : SchedWrite;
54 def WriteStore : SchedWrite;
55 def WriteMove : SchedWrite;
59 def WriteZero : SchedWrite;
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DARMSchedule.td31 // def WriteALUsr : SchedWrite;
32 // def ReadAdvanceALUsr : ScheRead;
35 // def ADDrs : I<>, Sched<[WriteALUsr, ReadAdvanceALUsr, ReadDefault,
44 // def P01 : ProcResource<3>; // ALU unit (3 of it).
47 // def : WriteRes<WriteALUsr, [P01, P01]> {
54 // def : ReadAdvance<ReadAdvanceALUsr, 3>;
60 def WriteALU : SchedWrite;
61 def ReadALU : SchedRead;
64 def WriteALUsi : SchedWrite; // Shift by immediate.
65 def WriteALUsr : SchedWrite; // Shift by register.
[all …]
/aosp_15_r20/external/clang/include/clang/Basic/
H A DDiagnosticGroups.td10 def ImplicitFunctionDeclare : DiagGroup<"implicit-function-declaration">;
11 def ImplicitInt : DiagGroup<"implicit-int">;
14 def Implicit : DiagGroup<"implicit", [
20 def : DiagGroup<"abi">;
21 def AbsoluteValue : DiagGroup<"absolute-value">;
22 def AddressOfTemporary : DiagGroup<"address-of-temporary">;
23 def : DiagGroup<"aggregate-return">;
24 def GNUAlignofExpression : DiagGroup<"gnu-alignof-expression">;
25 def AmbigMemberTemplate : DiagGroup<"ambiguous-member-template">;
26 def GNUAnonymousStruct : DiagGroup<"gnu-anonymous-struct">;
[all …]
H A DDiagnosticSemaKinds.td17 def note_previous_decl : Note<"%0 declared here">;
18 def note_entity_declared_at : Note<"%0 declared here">;
19 def note_callee_decl : Note<"%0 declared here">;
20 def note_defined_here : Note<"%0 defined here">;
23 def warn_variables_not_in_loop_body : Warning<
27 def warn_redundant_loop_iteration : Warning<
31 def note_loop_iteration_here : Note<"%select{decremented|incremented}0 here">;
33 def warn_duplicate_enum_values : Warning<
36 def note_duplicate_element : Note<"element %0 also has value %1">;
39 def warn_unsigned_abs : Warning<
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/
H A DARMSchedule.td31 // def WriteALUsr : SchedWrite;
32 // def ReadAdvanceALUsr : ScheRead;
35 // def ADDrs : I<>, Sched<[WriteALUsr, ReadAdvanceALUsr, ReadDefault,
44 // def P01 : ProcResource<3>; // ALU unit (3 of it).
47 // def : WriteRes<WriteALUsr, [P01, P01]> {
54 // def : ReadAdvance<ReadAdvanceALUsr, 3>;
60 def WriteALU : SchedWrite;
61 def ReadALU : SchedRead;
64 def WriteALUsi : SchedWrite; // Shift by immediate.
65 def WriteALUsr : SchedWrite; // Shift by register.
[all …]
/aosp_15_r20/external/pytorch/torch/_C/
H A D__init__.pyi.in82 def __len__(self, /) -> builtins.int: ...
83 def __getitem__(self, index: builtins.int, /) -> _T_co | _NestedSequence[_T_co]: ...
84 def __contains__(self, x: builtins.object, /) -> builtins.bool: ...
85 def __iter__(self, /) -> Iterator[_T_co | _NestedSequence[_T_co]]: ...
86 def __reversed__(self, /) -> Iterator[_T_co | _NestedSequence[_T_co]]: ...
87 def count(self, value: Any, /) -> builtins.int: ...
88 def index(self, value: Any, /) -> builtins.int: ...
96 def __get__(self, instance, owner=None) -> device: ...
100 def __init__(self, device: DeviceLikeType) -> None: ...
102 def __init__(self, type: str, index: _int) -> None: ...
[all …]
/aosp_15_r20/external/llvm/lib/Target/ARM/
H A DARMSchedule.td32 // def WriteALUsr : SchedWrite;
33 // def ReadAdvanceALUsr : ScheRead;
36 // def ADDrs : I<>, Sched<[WriteALUsr, ReadAdvanceALUsr, ReadDefault,
45 // def P01 : ProcResource<3>; // ALU unit (3 of it).
48 // def : WriteRes<WriteALUsr, [P01, P01]> {
55 // def : ReadAdvance<ReadAdvanceALUsr, 3>;
58 def WriteALU : SchedWrite;
59 def ReadALU : SchedRead;
62 def WriteALUsi : SchedWrite; // Shift by immediate.
63 def WriteALUsr : SchedWrite; // Shift by register.
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AVR/
H A DAVRDevices.td34 def FeatureSRAM : SubtargetFeature<"sram", "m_hasSRAM", "true",
38 def FeatureJMPCALL : SubtargetFeature<"jmpcall", "m_hasJMPCALL", "true",
43 def FeatureIJMPCALL : SubtargetFeature<"ijmpcall", "m_hasIJMPCALL", "true",
48 def FeatureEIJMPCALL : SubtargetFeature<"eijmpcall", "m_hasEIJMPCALL", "true",
53 def FeatureADDSUBIW : SubtargetFeature<"addsubiw", "m_hasADDSUBIW", "true",
58 def FeatureSmallStack
64 def FeatureMOVW : SubtargetFeature<"movw", "m_hasMOVW", "true",
70 def FeaturePROGMEM : SubtargetFeature<"progmem", "m_hasPROGMEM", "true",
74 def FeatureLPM : SubtargetFeature<"lpm", "m_hasLPM", "true",
78 def FeatureLPMX : SubtargetFeature<"lpmx", "m_hasLPMX", "true",
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Mips/
H A DMipsScheduleGeneric.td16 def MipsGenericModel : SchedMachineModel {
39 def GenericALU : ProcResource<1> { let BufferSize = 1; }
40 def GenericIssueALU : ProcResource<1> { let Super = GenericALU; }
42 def GenericWriteALU : SchedWriteRes<[GenericIssueALU]>;
47 def : InstRW<[GenericWriteALU], (instrs ADD, ADDi, ADDiu, ADDu, AND, ANDi,
53 def : InstRW<[GenericWriteALU], (instrs COPY)>;
59 def : InstRW<[GenericWriteALU], (instrs ADDIUPC, ALIGN, ALUIPC, AUI,
66 def : InstRW<[GenericWriteALU], (instrs AddiuRxImmX16, AddiuRxRxImm16,
82 def : InstRW<[GenericWriteALU], (instrs Constant32, LwConstant32,
88 def : InstRW<[GenericWriteALU], (instrs ADDIUPC_MM, ADDIUR1SP_MM, ADDIUR2_MM,
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
H A DMipsScheduleGeneric.td16 def MipsGenericModel : SchedMachineModel {
39 def GenericALU : ProcResource<1> { let BufferSize = 1; }
40 def GenericIssueALU : ProcResource<1> { let Super = GenericALU; }
42 def GenericWriteALU : SchedWriteRes<[GenericIssueALU]>;
47 def : InstRW<[GenericWriteALU], (instrs ADD, ADDi, ADDiu, ADDu, AND, ANDi,
53 def : InstRW<[GenericWriteALU], (instrs COPY)>;
59 def : InstRW<[GenericWriteALU], (instrs ADDIUPC, ALIGN, ALUIPC, AUI,
66 def : InstRW<[GenericWriteALU], (instrs AddiuRxImmX16, AddiuRxRxImm16,
82 def : InstRW<[GenericWriteALU], (instrs Constant32, LwConstant32,
88 def : InstRW<[GenericWriteALU], (instrs ADDIUPC_MM, ADDIUR1SP_MM, ADDIUR2_MM,
[all …]
/aosp_15_r20/external/llvm/lib/Target/Hexagon/
H A DHexagonIntrinsics.td227 def : T_RR_pat <M2_mpy_ll_s1, int_hexagon_M2_mpy_ll_s1>;
228 def : T_RR_pat <M2_mpy_ll_s0, int_hexagon_M2_mpy_ll_s0>;
229 def : T_RR_pat <M2_mpy_lh_s1, int_hexagon_M2_mpy_lh_s1>;
230 def : T_RR_pat <M2_mpy_lh_s0, int_hexagon_M2_mpy_lh_s0>;
231 def : T_RR_pat <M2_mpy_hl_s1, int_hexagon_M2_mpy_hl_s1>;
232 def : T_RR_pat <M2_mpy_hl_s0, int_hexagon_M2_mpy_hl_s0>;
233 def : T_RR_pat <M2_mpy_hh_s1, int_hexagon_M2_mpy_hh_s1>;
234 def : T_RR_pat <M2_mpy_hh_s0, int_hexagon_M2_mpy_hh_s0>;
236 def : T_RR_pat <M2_mpyu_ll_s1, int_hexagon_M2_mpyu_ll_s1>;
237 def : T_RR_pat <M2_mpyu_ll_s0, int_hexagon_M2_mpyu_ll_s0>;
[all …]
/aosp_15_r20/external/clang/include/clang/Driver/
H A DOptions.td22 def DriverOption : OptionFlag;
25 def LinkerInput : OptionFlag;
30 def NoArgumentUnused : OptionFlag;
34 def Unsupported : OptionFlag;
38 def CoreOption : OptionFlag;
42 def CLOption : OptionFlag;
45 def CC1Option : OptionFlag;
48 def CC1AsOption : OptionFlag;
51 def NoDriverOption : OptionFlag;
58 def CompileOnly_Group : OptionGroup<"<CompileOnly group>">;
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
H A DAVRDevices.td35 def FeatureSRAM : SubtargetFeature<"sram", "m_hasSRAM", "true",
39 def FeatureJMPCALL : SubtargetFeature<"jmpcall", "m_hasJMPCALL", "true",
45 def FeatureIJMPCALL : SubtargetFeature<"ijmpcall", "m_hasIJMPCALL",
51 def FeatureEIJMPCALL : SubtargetFeature<"eijmpcall", "m_hasEIJMPCALL",
56 def FeatureADDSUBIW : SubtargetFeature<"addsubiw", "m_hasADDSUBIW",
61 def FeatureSmallStack : SubtargetFeature<"smallstack", "m_hasSmallStack",
66 def FeatureMOVW : SubtargetFeature<"movw", "m_hasMOVW", "true",
71 def FeatureLPM : SubtargetFeature<"lpm", "m_hasLPM", "true",
75 def FeatureLPMX : SubtargetFeature<"lpmx", "m_hasLPMX", "true",
80 def FeatureELPM : SubtargetFeature<"elpm", "m_hasELPM", "true",
[all …]

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