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/linux-6.14.4/drivers/gpu/drm/amd/display/dc/resource/dcn20/
Ddcn20_resource.c28 #include "dc.h"
132 #define SRI(reg_name, block, id)\ argument
133 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
134 mm ## block ## id ## _ ## reg_name
136 #define SRI2_DWB(reg_name, block, id)\ argument
142 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ argument
145 #define SRIR(var_name, reg_name, block, id)\ argument
146 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
147 mm ## block ## id ## _ ## reg_name
149 #define SRII(reg_name, block, id)\ argument
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/linux-6.14.4/drivers/gpu/drm/amd/display/dc/resource/dce110/
Ddce110_resource.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
57 dc->ctx->logger
118 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
119 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
122 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
123 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
126 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
127 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
130 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
131 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
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/linux-6.14.4/drivers/gpu/drm/amd/display/dc/resource/dcn10/
Ddcn10_resource.c27 #include "dc.h"
115 #define SRI(reg_name, block, id)\ argument
116 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
117 mm ## block ## id ## _ ## reg_name
120 #define SRII(reg_name, block, id)\ argument
121 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
122 mm ## block ## id ## _ ## reg_name
124 #define VUPDATE_SRII(reg_name, block, id)\ argument
125 .reg_name[id] = BASE(mm ## reg_name ## 0 ## _ ## block ## id ## _BASE_IDX) + \
126 mm ## reg_name ## 0 ## _ ## block ## id
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/linux-6.14.4/drivers/gpu/drm/amd/display/dc/resource/dcn32/
Ddcn32_resource.c1 // SPDX-License-Identifier: MIT
28 #include "dc.h"
112 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
119 #define SR_ARR(reg_name, id) \ argument
120 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
122 #define SR_ARR_INIT(reg_name, id, value) \ argument
123 REG_STRUCT[id].reg_name = value
125 #define SRI(reg_name, block, id)\ argument
126 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
127 reg ## block ## id ## _ ## reg_name
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/linux-6.14.4/Documentation/devicetree/bindings/display/bridge/
Dfsl,imx8qxp-pixel-link.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <[email protected]>
27 - fsl,imx8qm-dc-pixel-link
28 - fsl,imx8qxp-dc-pixel-link
30 fsl,dc-id:
36 fsl,dc-stream-id:
39 u8 value representing the display controller stream index that the pixel
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/linux-6.14.4/drivers/gpu/drm/amd/display/dc/link/
Dlink_dpms.c27 * This file owns the programming sequence of stream's dpms state associated
28 * with the link and link's enable/disable sequences as result of the stream's
31 * TODO - The reason link owns stream's dpms programming sequence is
34 * stream state programming sequence. This creates a gray area where the
35 * boundary between link and stream is not clearly defined.
77 void link_blank_all_dp_displays(struct dc *dc) in link_blank_all_dp_displays() argument
83 for (i = 0; i < dc->link_count; i++) { in link_blank_all_dp_displays()
84 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) || in link_blank_all_dp_displays()
85 (dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL)) in link_blank_all_dp_displays()
89 dp_retrieve_lttpr_cap(dc->links[i]); in link_blank_all_dp_displays()
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/linux-6.14.4/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
Ddce110_clk_mgr.c2 * Copyright 2012-16 Advanced Micro Devices, Inc.
39 #define SRI(reg_name, block, id)\ argument
40 .reg_name = mm ## block ## id ## _ ## reg_name
55 /*ClocksStateInvalid - should not be used*/
57 /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
67 const struct dc *dc, in determine_sclk_from_bounding_box() argument
76 if (dc->sclk_lvls.num_levels == 0) in determine_sclk_from_bounding_box()
79 for (i = 0; i < dc->sclk_lvls.num_levels; i++) { in determine_sclk_from_bounding_box()
80 if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk) in determine_sclk_from_bounding_box()
81 return dc->sclk_lvls.clocks_in_khz[i]; in determine_sclk_from_bounding_box()
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/linux-6.14.4/drivers/gpu/drm/amd/display/dc/resource/dcn401/
Ddcn401_resource.c1 // SPDX-License-Identifier: MIT
6 #include "dc.h"
98 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
105 #define SR_ARR(reg_name, id)\ argument
106 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
108 #define SR_ARR_INIT(reg_name, id, value)\ argument
109 REG_STRUCT[id].reg_name = value
111 #define SRI(reg_name, block, id)\ argument
112 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
113 reg ## block ## id ## _ ## reg_name
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/linux-6.14.4/drivers/gpu/drm/amd/display/dc/core/
Ddc_link_enc_cfg.c29 #define DC_LOGGER dc->ctx->logger
31 /* Check whether stream is supported by DIG link encoders. */
32 static bool is_dig_link_enc_stream(struct dc_stream_state *stream) in is_dig_link_enc_stream() argument
39 if (stream) { in is_dig_link_enc_stream()
40 for (i = 0; i < stream->ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in is_dig_link_enc_stream()
41 link_enc = stream->ctx->dc->res_pool->link_encoders[i]; in is_dig_link_enc_stream()
43 /* Need to check link signal type rather than stream signal type which may not in is_dig_link_enc_stream()
46 if (link_enc && ((uint32_t)stream->link->connector_signal & link_enc->output_signals)) { in is_dig_link_enc_stream()
47 if (dc_is_dp_signal(stream->signal)) { in is_dig_link_enc_stream()
51 stream->ctx->dc->link_srv->dp_decide_link_settings(stream, &link_settings); in is_dig_link_enc_stream()
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Ddc_state.c42 dc->ctx->logger
49 if (state->phantom_stream_count >= MAX_PHANTOM_PIPES) in dc_state_track_phantom_stream()
52 state->phantom_streams[state->phantom_stream_count++] = phantom_stream; in dc_state_track_phantom_stream()
62 /* first find phantom stream in the dc_state */ in dc_state_untrack_phantom_stream()
63 for (i = 0; i < state->phantom_stream_count; i++) { in dc_state_untrack_phantom_stream()
64 if (state->phantom_streams[i] == phantom_stream) { in dc_state_untrack_phantom_stream()
65 state->phantom_streams[i] = NULL; in dc_state_untrack_phantom_stream()
71 /* failed to find stream in state */ in dc_state_untrack_phantom_stream()
76 state->phantom_stream_count--; in dc_state_untrack_phantom_stream()
77 for (; i < state->phantom_stream_count; i++) in dc_state_untrack_phantom_stream()
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Ddc_resource.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
95 dc->ctx->logger
100 #define UNABLE_TO_SPLIT -1
220 struct resource_pool *dc_create_resource_pool(struct dc *dc, in dc_create_resource_pool() argument
230 init_data->num_virtual_links, dc); in dc_create_resource_pool()
234 init_data->num_virtual_links, dc); in dc_create_resource_pool()
238 init_data->num_virtual_links, dc); in dc_create_resource_pool()
243 init_data->num_virtual_links, dc); in dc_create_resource_pool()
247 init_data->num_virtual_links, dc); in dc_create_resource_pool()
251 init_data->num_virtual_links, dc); in dc_create_resource_pool()
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Ddc.c29 #include "dc.h"
90 dc->ctx
93 dc->ctx->logger
95 static const char DC_BUILD_ID[] = "production-build";
100 * DC is the OS-agnostic component of the amdgpu DC driver.
102 * DC maintains and validates a set of structs representing the state of the
105 * Main DC HW structs:
107 * struct dc - The central struct. One per driver. Created on driver load,
110 * struct dc_context - One per driver.
111 * Used as a backpointer by most other structs in dc.
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/linux-6.14.4/drivers/gpu/drm/amd/display/dc/resource/dce112/
Ddce112_resource.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
63 dc->ctx->logger
119 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
120 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
123 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
124 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
127 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
128 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
131 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
132 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
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/linux-6.14.4/drivers/gpu/drm/amd/display/dc/inc/
Dcore_types.h29 #include "dc.h"
83 struct dc *dc,
87 struct dc *dc, struct dc_state *context,
92 struct dc *dc, struct dc_state *context);
95 const struct dc *dc,
98 struct dc *dc,
101 * @populate_dml_pipes - Populate pipe data struct
107 struct dc *dc,
119 struct dc *dc,
124 * Unassign a link encoder from a stream.
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/linux-6.14.4/drivers/gpu/drm/amd/display/dc/link/hwss/
Dlink_hwss_dio.c42 struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc; in set_dio_throttled_vcp_size()
44 stream_encoder->funcs->set_throttled_vcp_size( in set_dio_throttled_vcp_size()
51 struct link_encoder *link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link); in setup_dio_stream_encoder()
52 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; in setup_dio_stream_encoder()
54 link_enc->funcs->connect_dig_be_to_fe(link_enc, in setup_dio_stream_encoder()
55 pipe_ctx->stream_res.stream_enc->id, true); in setup_dio_stream_encoder()
56 if (dc_is_dp_signal(pipe_ctx->stream->signal)) in setup_dio_stream_encoder()
57 pipe_ctx->stream->ctx->dc->link_srv->dp_trace_source_sequence(pipe_ctx->stream->link, in setup_dio_stream_encoder()
59 if (stream_enc->funcs->enable_stream) in setup_dio_stream_encoder()
60 stream_enc->funcs->enable_stream(stream_enc, in setup_dio_stream_encoder()
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/linux-6.14.4/drivers/gpu/drm/amd/display/dc/hwss/dce110/
Ddce110_hwseq.c27 #include "dc.h"
74 * For eDP, after power-up/power/down,
84 hws->ctx
87 ctx->logger
89 struct dc_context *ctx = dc->ctx
92 hws->regs->reg
96 hws->shifts->field_name, hws->masks->field_name
104 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
107 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
110 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
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/linux-6.14.4/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm.c30 #include "dc.h"
32 #include "dc/inc/core_types.h"
35 #include "dc/inc/hw/dmcu.h"
36 #include "dc/inc/hw/abm.h"
37 #include "dc/dc_dmub_srv.h"
38 #include "dc/dc_edid_parser.h"
39 #include "dc/dc_stat.h"
40 #include "dc/dc_state.h"
101 #include <media/cec-notifier.h>
171 * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
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Damdgpu_dm_crtc.c1 // SPDX-License-Identifier: MIT
29 #include "dc.h"
43 struct drm_crtc *crtc = &acrtc->base; in amdgpu_dm_crtc_handle_vblank()
44 struct drm_device *dev = crtc->dev; in amdgpu_dm_crtc_handle_vblank()
49 spin_lock_irqsave(&dev->event_lock, flags); in amdgpu_dm_crtc_handle_vblank()
51 /* Send completion event for cursor-only commits */ in amdgpu_dm_crtc_handle_vblank()
52 if (acrtc->event && acrtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { in amdgpu_dm_crtc_handle_vblank()
53 drm_crtc_send_vblank_event(crtc, acrtc->event); in amdgpu_dm_crtc_handle_vblank()
55 acrtc->event = NULL; in amdgpu_dm_crtc_handle_vblank()
58 spin_unlock_irqrestore(&dev->event_lock, flags); in amdgpu_dm_crtc_handle_vblank()
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/linux-6.14.4/drivers/gpu/drm/amd/display/dc/resource/dcn30/
Ddcn30_resource.c28 #include "dc.h"
95 dc->ctx->logger
121 #define SRI(reg_name, block, id)\ argument
122 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
123 mm ## block ## id ## _ ## reg_name
125 #define SRI2(reg_name, block, id)\ argument
129 #define SRIR(var_name, reg_name, block, id)\ argument
130 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
131 mm ## block ## id ## _ ## reg_name
133 #define SRII(reg_name, block, id)\ argument
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/linux-6.14.4/drivers/gpu/drm/amd/display/dc/link/protocols/
Dlink_edp_panel_control.c38 #include "dc/dc_dmub_srv.h"
43 link->ctx->logger
93 link->panel_mode = panel_mode; in dp_set_panel_mode()
96 link->link_index, in dp_set_panel_mode()
97 link->dpcd_caps.panel_mode_edp, in dp_set_panel_mode()
107 if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) { in dp_get_panel_mode()
109 switch (link->dpcd_caps.branch_dev_id) { in dp_get_panel_mode()
113 * provide sink device id, alternate scrambler in dp_get_panel_mode()
118 link->dpcd_caps.branch_dev_name, in dp_get_panel_mode()
121 link->dpcd_caps. in dp_get_panel_mode()
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/linux-6.14.4/drivers/gpu/drm/amd/display/dc/resource/dcn315/
Ddcn315_resource.c28 #include "dc.h"
166 #define SRI(reg_name, block, id)\ argument
167 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
168 reg ## block ## id ## _ ## reg_name
170 #define SRI2(reg_name, block, id)\ argument
174 #define SRIR(var_name, reg_name, block, id)\ argument
175 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
176 reg ## block ## id ## _ ## reg_name
178 #define SRII(reg_name, block, id)\ argument
179 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
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/linux-6.14.4/drivers/gpu/drm/amd/display/dc/dml2/
Ddml2_wrapper.h1 /* SPDX-License-Identifier: MIT */
36 struct dc;
72 struct dc *dc; member
75 …bool (*can_support_mclk_switch_using_fw_based_vblank_stretch)(struct dc *dc, struct dc_state *cont…
76 …bool (*acquire_secondary_pipe_for_mpc_odm)(const struct dc *dc, struct dc_state *state, struct pip…
81 const struct dc_stream_state *stream,
96 const struct dc_stream_state *stream);
105 const struct dc_stream_state *stream);
106 struct dc_stream_state *(*get_stream_from_id)(const struct dc_state *state, unsigned int id);
108 struct dc_stream_state *stream,
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Ddml2_utils.h1 /* SPDX-License-Identifier: MIT */
31 struct dc;
45 bool is_dtbclk_required(const struct dc *dc, struct dc_state *context);
46 bool dml2_is_stereo_timing(const struct dc_stream_state *stream);
53 * dml2_dc_construct_pipes - This function will determine if we need additional pipes based
58 * map_hw_resources(&s->cur_display_config, &s->mode_support_info);
59 …* result = dml_mode_programming(&in_ctx->dml_core_ctx, s->mode_support_params.out_lowest_state_idx…
60 * dml2_dc_construct_pipes(in_display_state, s->mode_support_info, out_hw_context);
64 * @context: To obtain res_ctx and read other information like stream ID etc.
75 * dml2_predict_pipe_split - This function is the dml2 version of predict split pipe. It predicts a
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/linux-6.14.4/drivers/gpu/drm/bridge/imx/
Dimx8qxp-pixel-link.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/media-bus-format.h>
18 #include <dt-bindings/firmware/imx/rsrc.h>
20 #define DRIVER_NAME "imx8qxp-display-pixel-link"
43 ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc, in imx8qxp_pixel_link_enable_mst_en()
44 pl->mst_en_ctrl, true); in imx8qxp_pixel_link_enable_mst_en()
46 DRM_DEV_ERROR(pl->dev, in imx8qxp_pixel_link_enable_mst_en()
47 "failed to enable DC%u stream%u pixel link mst_en: %d\n", in imx8qxp_pixel_link_enable_mst_en()
48 pl->dc_id, pl->stream_id, ret); in imx8qxp_pixel_link_enable_mst_en()
55 ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc, in imx8qxp_pixel_link_enable_mst_vld()
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/linux-6.14.4/drivers/gpu/drm/amd/display/dc/resource/dce100/
Ddce100_resource.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
109 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
110 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
113 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
114 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
117 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
118 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
121 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
122 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
125 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
[all …]

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