| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| D | dcn303_resource.c | 1 // SPDX-License-Identifier: MIT
78 dc->ctx->logger
97 .dwb_fi_phase = -1, // -1 = disable,
178 #define SRI(reg_name, block, id)\ argument
179 ….reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_…
181 #define SRI2(reg_name, block, id)\ argument
184 #define SRII(reg_name, block, id)\ argument
185 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
186 mm ## block ## id ## _ ## reg_name
188 #define DCCG_SRII(reg_name, block, id)\ argument
[all …]
|
| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| D | dcn401_resource.c | 1 // SPDX-License-Identifier: MIT
6 #include "dc.h"
98 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
105 #define SR_ARR(reg_name, id)\ argument
106 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
108 #define SR_ARR_INIT(reg_name, id, value)\ argument
109 REG_STRUCT[id].reg_name = value
111 #define SRI(reg_name, block, id)\ argument
112 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
113 reg ## block ## id ## _ ## reg_name
[all …]
|
| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| D | dcn302_resource.c | 78 dc->ctx->logger
96 .dwb_fi_phase = -1, // -1 = disable,
181 #define SRI(reg_name, block, id)\ argument
182 ….reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_…
184 #define SRI2(reg_name, block, id)\ argument
187 #define SRII(reg_name, block, id)\ argument
188 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
189 mm ## block ## id ## _ ## reg_name
191 #define DCCG_SRII(reg_name, block, id)\ argument
192 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
[all …]
|
| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| D | dcn321_resource.c | 1 // SPDX-License-Identifier: MIT
28 #include "dc.h"
113 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
120 #define SR_ARR(reg_name, id)\ argument
121 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
123 #define SR_ARR_INIT(reg_name, id, value)\ argument
124 REG_STRUCT[id].reg_name = value
126 #define SRI(reg_name, block, id)\ argument
127 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
128 reg ## block ## id ## _ ## reg_name
[all …]
|
| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| D | dcn32_resource.c | 1 // SPDX-License-Identifier: MIT
28 #include "dc.h"
112 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
119 #define SR_ARR(reg_name, id) \ argument
120 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
122 #define SR_ARR_INIT(reg_name, id, value) \ argument
123 REG_STRUCT[id].reg_name = value
125 #define SRI(reg_name, block, id)\ argument
126 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
127 reg ## block ## id ## _ ## reg_name
[all …]
|
| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/resource/dcn301/ |
| D | dcn301_resource.c | 2 * Copyright 2019-2021 Advanced Micro Devices, Inc.
28 #include "dc.h"
96 dc->ctx->logger
120 #define SRI(reg_name, block, id)\ argument
121 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
122 mm ## block ## id ## _ ## reg_name
124 #define SRI2(reg_name, block, id)\ argument
128 #define SRIR(var_name, reg_name, block, id)\ argument
129 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
130 mm ## block ## id ## _ ## reg_name
[all …]
|
| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| D | dcn35_resource.c | 1 /* SPDX-License-Identifier: MIT */
28 #include "dc.h"
127 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
135 #define SR_ARR(reg_name, id) \ argument
136 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
138 #define SR_ARR_INIT(reg_name, id, value) \ argument
139 REG_STRUCT[id].reg_name = value
141 #define SRI(reg_name, block, id)\ argument
142 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
143 reg ## block ## id ## _ ## reg_name
[all …]
|
| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| D | dcn21_resource.c | 30 #include "dc.h"
105 #define SRI(reg_name, block, id)\ argument
106 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
107 mm ## block ## id ## _ ## reg_name
109 #define SRIR(var_name, reg_name, block, id)\ argument
110 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
111 mm ## block ## id ## _ ## reg_name
113 #define SRII(reg_name, block, id)\ argument
114 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
115 mm ## block ## id ## _ ## reg_name
[all …]
|
| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| D | dcn31_resource.c | 28 #include "dc.h"
107 dc->ctx->logger
132 #define SRI(reg_name, block, id)\ argument
133 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
134 reg ## block ## id ## _ ## reg_name
136 #define SRI2(reg_name, block, id)\ argument
140 #define SRIR(var_name, reg_name, block, id)\ argument
141 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
142 reg ## block ## id ## _ ## reg_name
144 #define SRII(reg_name, block, id)\ argument
[all …]
|
| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| D | dcn351_resource.c | 1 /* SPDX-License-Identifier: MIT */
6 #include "dc.h"
107 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
115 #define SR_ARR(reg_name, id) \ argument
116 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
118 #define SR_ARR_INIT(reg_name, id, value) \ argument
119 REG_STRUCT[id].reg_name = value
121 #define SRI(reg_name, block, id)\ argument
122 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
123 reg ## block ## id ## _ ## reg_name
[all …]
|
| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| D | dcn30_resource.c | 28 #include "dc.h"
95 dc->ctx->logger
121 #define SRI(reg_name, block, id)\ argument
122 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
123 mm ## block ## id ## _ ## reg_name
125 #define SRI2(reg_name, block, id)\ argument
129 #define SRIR(var_name, reg_name, block, id)\ argument
130 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
131 mm ## block ## id ## _ ## reg_name
133 #define SRII(reg_name, block, id)\ argument
[all …]
|
| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| D | dcn201_resource.c | 27 #include "dc.h"
255 #define SRI(reg_name, block, id)\ argument
256 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
257 mm ## block ## id ## _ ## reg_name
259 #define SRIR(var_name, reg_name, block, id)\ argument
260 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
261 mm ## block ## id ## _ ## reg_name
263 #define SRII(reg_name, block, id)\ argument
264 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
265 mm ## block ## id ## _ ## reg_name
[all …]
|
| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| D | dcn314_resource.c | 1 // SPDX-License-Identifier: MIT
29 #include "dc.h"
122 dc->ctx->logger
149 #define SRI(reg_name, block, id)\ argument
150 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
151 reg ## block ## id ## _ ## reg_name
153 #define SRI2(reg_name, block, id)\ argument
157 #define SRIR(var_name, reg_name, block, id)\ argument
158 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
159 reg ## block ## id ## _ ## reg_name
[all …]
|
| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
| D | dcn10_resource.c | 27 #include "dc.h"
115 #define SRI(reg_name, block, id)\ argument
116 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
117 mm ## block ## id ## _ ## reg_name
120 #define SRII(reg_name, block, id)\ argument
121 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
122 mm ## block ## id ## _ ## reg_name
124 #define VUPDATE_SRII(reg_name, block, id)\ argument
125 .reg_name[id] = BASE(mm ## reg_name ## 0 ## _ ## block ## id ## _BASE_IDX) + \
126 mm ## reg_name ## 0 ## _ ## block ## id
[all …]
|
| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| D | dcn20_resource.c | 28 #include "dc.h"
132 #define SRI(reg_name, block, id)\ argument
133 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
134 mm ## block ## id ## _ ## reg_name
136 #define SRI2_DWB(reg_name, block, id)\ argument
142 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ argument
145 #define SRIR(var_name, reg_name, block, id)\ argument
146 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
147 mm ## block ## id ## _ ## reg_name
149 #define SRII(reg_name, block, id)\ argument
[all …]
|
| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/resource/dce80/ |
| D | dce80_resource.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
113 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
114 .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL),
116 - mmDPG_WATERMARK_MASK_CONTROL),
119 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
120 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
122 - mmDPG_WATERMARK_MASK_CONTROL),
125 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
126 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
128 - mmDPG_WATERMARK_MASK_CONTROL),
[all …]
|
| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/resource/dce112/ |
| D | dce112_resource.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
63 dc->ctx->logger
119 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
120 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
123 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
124 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
127 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
128 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
131 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
132 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
[all …]
|
| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| D | dcn316_resource.c | 28 #include "dc.h"
152 #define SRI(reg_name, block, id)\ argument
153 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
154 reg ## block ## id ## _ ## reg_name
156 #define SRI2(reg_name, block, id)\ argument
160 #define SRIR(var_name, reg_name, block, id)\ argument
161 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
162 reg ## block ## id ## _ ## reg_name
164 #define SRII(reg_name, block, id)\ argument
165 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
[all …]
|
| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/dce60/ |
| D | dce60_resource.c | 114 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
115 .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL),
117 - mmDPG_PIPE_ARBITRATION_CONTROL3),
120 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
121 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
123 - mmDPG_PIPE_ARBITRATION_CONTROL3),
126 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
127 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
129 - mmDPG_PIPE_ARBITRATION_CONTROL3),
132 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
[all …]
|
| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| D | dcn315_resource.c | 28 #include "dc.h"
166 #define SRI(reg_name, block, id)\ argument
167 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
168 reg ## block ## id ## _ ## reg_name
170 #define SRI2(reg_name, block, id)\ argument
174 #define SRIR(var_name, reg_name, block, id)\ argument
175 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
176 reg ## block ## id ## _ ## reg_name
178 #define SRII(reg_name, block, id)\ argument
179 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
[all …]
|
| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/resource/dce110/ |
| D | dce110_resource.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
57 dc->ctx->logger
118 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
119 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
122 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
123 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
126 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
127 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
130 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
131 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
[all …]
|
| /linux-6.14.4/Documentation/devicetree/bindings/display/bridge/ |
| D | fsl,imx8qxp-pixel-link.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <[email protected]>
27 - fsl,imx8qm-dc-pixel-link
28 - fsl,imx8qxp-dc-pixel-link
30 fsl,dc-id:
36 fsl,dc-stream-id:
52 "^port@[1-4]$":
[all …]
|
| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/resource/dce120/ |
| D | dce120_resource.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.cls
101 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
104 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
107 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
110 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
113 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
116 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
140 #define SRI(reg_name, block, id)\ argument
141 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
142 mm ## block ## id ## _ ## reg_name
[all …]
|
| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/resource/dce100/ |
| D | dce100_resource.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
109 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
110 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
113 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
114 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
117 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
118 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
121 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
122 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
125 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
[all …]
|
| /linux-6.14.4/drivers/gpu/drm/atmel-hlcdc/ |
| D | atmel_hlcdc_dc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 * Author: Jean-Jacques Hiblot <[email protected]>
8 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
14 #include <linux/mfd/atmel-hlcdc.h>
40 .id = 0,
71 .id = 0,
87 .id = 1,
103 .name = "high-end-overlay",
106 .id = 2,
128 .id = 3,
[all …]
|