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/linux-6.14.4/arch/loongarch/kvm/intc/
Deiointc.c1 // SPDX-License-Identifier: GPL-2.0
12 int ipnum, cpu, irq_index, irq_mask, irq; in eiointc_set_sw_coreisr() local
15 ipnum = s->ipmap.reg_u8[irq / 32]; in eiointc_set_sw_coreisr()
16 if (!(s->status & BIT(EIOINTC_ENABLE_INT_ENCODE))) { in eiointc_set_sw_coreisr()
23 cpu = s->coremap.reg_u8[irq]; in eiointc_set_sw_coreisr()
24 if (!!(s->coreisr.reg_u32[cpu][irq_index] & irq_mask)) in eiointc_set_sw_coreisr()
25 set_bit(irq, s->sw_coreisr[cpu][ipnum]); in eiointc_set_sw_coreisr()
27 clear_bit(irq, s->sw_coreisr[cpu][ipnum]); in eiointc_set_sw_coreisr()
33 int ipnum, cpu, found, irq_index, irq_mask; in eiointc_update_irq() local
37 ipnum = s->ipmap.reg_u8[irq / 32]; in eiointc_update_irq()
[all …]
Dipi.c1 // SPDX-License-Identifier: GPL-2.0
12 int cpu, action; in ipi_send() local
17 cpu = ((data & 0xffffffff) >> 16) & 0x3ff; in ipi_send()
18 vcpu = kvm_get_vcpu_by_cpuid(kvm, cpu); in ipi_send()
20 kvm_err("%s: invalid target cpu: %d\n", __func__, cpu); in ipi_send()
25 spin_lock(&vcpu->arch.ipi_state.lock); in ipi_send()
26 status = vcpu->arch.ipi_state.status; in ipi_send()
27 vcpu->arch.ipi_state.status |= action; in ipi_send()
28 spin_unlock(&vcpu->arch.ipi_state.lock); in ipi_send()
40 spin_lock(&vcpu->arch.ipi_state.lock); in ipi_clear()
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/linux-6.14.4/drivers/thermal/intel/
Dintel_tcc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * intel_tcc.c - Library for Intel TCC (thermal control circuitry) MSR access
10 #include <asm/intel-family.h>
14 * struct temp_masks - Bitmasks for temperature readings
15 * @tcc_offset: TCC offset in MSR_TEMPERATURE_TARGET
129 memcpy(&intel_tcc_temp_masks, (const void *)id->driver_data, in intel_tcc_init()
141 * intel_tcc_get_offset_mask() - Returns the bitmask to read TCC offset
143 * Get the model-specific bitmask to extract TCC_OFFSET from the MSR
145 * not support TCC offset.
147 * Return: The model-specific bitmask for TCC offset.
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/linux-6.14.4/tools/testing/selftests/rseq/
Dparam_test.c1 // SPDX-License-Identifier: LGPL-2.1
44 static __thread __attribute__((tls_model("initial-exec")))
49 static __thread __attribute__((tls_model("initial-exec"), unused))
113 "ahi %%" INJECT_ASM_REG ", -1\n\t" \
204 "addiu " INJECT_ASM_REG ", -1\n\t" \
226 "addi " INJECT_ASM_REG "," INJECT_ASM_REG ", -1\n\t" \
250 "l.addi " INJECT_ASM_REG "," INJECT_ASM_REG ", -1\n\t" \
269 if (loc_nr_loops == -1 && opt_modulo) { \
270 if (yield_mod_cnt == opt_modulo - 1) { \
326 int rseq_membarrier_expedited(int cpu) in rseq_membarrier_expedited() argument
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/linux-6.14.4/arch/arm/mach-zynq/
Dslcr.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2011-2013 Xilinx Inc.
18 #define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */
33 * zynq_slcr_write - Write to a register in SLCR block
36 * @offset: Register offset in SLCR block
40 static int zynq_slcr_write(u32 val, u32 offset) in zynq_slcr_write() argument
42 return regmap_write(zynq_slcr_regmap, offset, val); in zynq_slcr_write()
46 * zynq_slcr_read - Read a register in SLCR block
49 * @offset: Register offset in SLCR block
53 static int zynq_slcr_read(u32 *val, u32 offset) in zynq_slcr_read() argument
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/linux-6.14.4/Documentation/core-api/
Dthis_cpu_ops.rst8 this_cpu operations are a way of optimizing access to per cpu
11 the cpu permanently stored the beginning of the per cpu area for a
14 this_cpu operations add a per cpu variable offset to the processor
15 specific per cpu base and encode that operation in the instruction
16 operating on the per cpu variable.
19 the offset and the operation on the data. Therefore it is not
24 Read-modify-write operations are of particular interest. Frequently
32 synchronization is not necessary since we are dealing with per cpu
37 Please note that accesses by remote processors to a per cpu area are
65 ------------------------------------
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/linux-6.14.4/drivers/gpio/
Dgpio-mvebu.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
15 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
19 * - the basic variant, called "orion-gpio", with the simplest
21 * non-SMP Discovery systems
22 * - the mv78200 variant for MV78200 Discovery systems. This variant
26 * - the armadaxp variant for Armada XP systems. This variant keeps
28 * interrupts are used, but adds per-CPU cause/edge mask/level mask
29 * registers n a separate memory area for the per-CPU GPIO
78 /* The MV78200 has per-CPU registers for edge mask and level mask */
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/linux-6.14.4/drivers/gpu/drm/i915/gem/selftests/
Di915_gem_coherency.c2 * SPDX-License-Identifier: MIT
23 static int cpu_set(struct context *ctx, unsigned long offset, u32 v) in cpu_set() argument
27 u32 *cpu; in cpu_set() local
30 i915_gem_object_lock(ctx->obj, NULL); in cpu_set()
31 err = i915_gem_object_prepare_write(ctx->obj, &needs_clflush); in cpu_set()
35 page = i915_gem_object_get_page(ctx->obj, offset >> PAGE_SHIFT); in cpu_set()
36 cpu = kmap_local_page(page) + offset_in_page(offset); in cpu_set()
39 drm_clflush_virt_range(cpu, sizeof(*cpu)); in cpu_set()
41 *cpu = v; in cpu_set()
44 drm_clflush_virt_range(cpu, sizeof(*cpu)); in cpu_set()
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/linux-6.14.4/tools/testing/selftests/kvm/lib/arm64/
Dgic_v3.c1 // SPDX-License-Identifier: GPL-2.0
48 GUEST_ASSERT(count--); in gicv3_gicd_wait_for_rwp()
53 static inline volatile void *gicr_base_cpu(uint32_t cpu) in gicr_base_cpu() argument
56 return GICR_BASE_GVA + cpu * SZ_64K * 2; in gicr_base_cpu()
59 static void gicv3_gicr_wait_for_rwp(uint32_t cpu) in gicv3_gicr_wait_for_rwp() argument
63 while (readl(gicr_base_cpu(cpu) + GICR_CTLR) & GICR_CTLR_RWP) { in gicv3_gicr_wait_for_rwp()
64 GUEST_ASSERT(count--); in gicv3_gicr_wait_for_rwp()
124 * All other fields are read-only, so no need to read CTLR first. In in gicv3_set_eoi_split()
132 uint32_t gicv3_reg_readl(uint32_t cpu_or_dist, uint64_t offset) in gicv3_reg_readl() argument
136 return readl(base + offset); in gicv3_reg_readl()
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/linux-6.14.4/arch/x86/include/asm/uv/
Duv_hub.h9 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
33 * M - The low M bits of a physical address represent the offset
38 * N - Number of bits in the node portion of a socket physical
41 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
44 * right shift the NASID by 1 to exclude the always-zero bit.
47 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
50 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
53 * GPA - (global physical address) a socket physical address converted
62 * +--------------------------------+---------------------+
64 * +--------------------------------+---------------------+
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/linux-6.14.4/kernel/time/
Dtimer_list.c1 // SPDX-License-Identifier: GPL-2.0
18 #include "tick-internal.h"
21 int cpu; member
28 * to the console (on SysRq-Q):
49 SEQ_printf(m, " #%d: <%pK>, %ps", idx, taddr, timer->function); in print_timer()
50 SEQ_printf(m, ", S:%02x", timer->state); in print_timer()
52 SEQ_printf(m, " # expires at %Lu-%Lu nsecs [in %Ld to %Ld nsecs]\n", in print_timer()
55 (long long)(ktime_to_ns(hrtimer_get_softexpires(timer)) - now), in print_timer()
56 (long long)(ktime_to_ns(hrtimer_get_expires(timer)) - now)); in print_timer()
73 raw_spin_lock_irqsave(&base->cpu_base->lock, flags); in print_active_timers()
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/linux-6.14.4/drivers/clk/qcom/
Dkrait-cc.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/clk-provider.h>
16 #include "clk-krait.h"
52 mux->old_index = krait_mux_clk_ops.get_parent(&mux->hw); in krait_notifier_cb()
53 ret = krait_mux_clk_ops.set_parent(&mux->hw, mux->safe_sel); in krait_notifier_cb()
54 mux->reparent = false; in krait_notifier_cb()
61 if (!mux->reparent) in krait_notifier_cb()
62 ret = krait_mux_clk_ops.set_parent(&mux->hw, in krait_notifier_cb()
63 mux->old_index); in krait_notifier_cb()
74 mux->clk_nb.notifier_call = krait_notifier_cb; in krait_notifier_register()
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/linux-6.14.4/drivers/gpu/drm/lima/
Dlima_vm.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /* Copyright 2017-2019 Qiang Yu <[email protected]> */
5 #include <linux/dma-mapping.h>
26 #define LIMA_VM_PT_MASK ((1 << LIMA_VM_PD_SHIFT) - 1)
27 #define LIMA_VM_BT_MASK ((1 << LIMA_VM_PB_SHIFT) - 1)
43 vm->bts[pbe].cpu[bte] = 0; in lima_vm_unmap_range()
52 if (!vm->bts[pbe].cpu) { in lima_vm_map_page()
57 vm->bts[pbe].cpu = dma_alloc_wc( in lima_vm_map_page()
58 vm->dev->dev, LIMA_PAGE_SIZE << LIMA_VM_NUM_PT_PER_BT_SHIFT, in lima_vm_map_page()
59 &vm->bts[pbe].dma, GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO); in lima_vm_map_page()
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/linux-6.14.4/tools/perf/pmu-events/
Dempty-pmu-events.c2 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <pmu-events/pmu-events.h>
12 int offset; member
22 /* offset=0 */ "tool\000"
23 /* offset=5 */ "duration_time\000tool\000Wall clock interval time in nanoseconds\000config=1\000\00…
24 /* offset=78 */ "user_time\000tool\000User (non-kernel) time in nanoseconds\000config=2\000\00000\0…
25 /* offset=145 */ "system_time\000tool\000System/kernel time in nanoseconds\000config=3\000\00000\00…
26 /* offset=210 */ "has_pmem\000tool\0001 if persistent memory installed otherwise 0\000config=4\000\…
27 …* offset=283 */ "num_cores\000tool\000Number of cores. A core consists of 1 or more thread, with e…
28 /* offset=425 */ "num_cpus\000tool\000Number of logical Linux CPUs. There may be multiple such CPUs…
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/linux-6.14.4/arch/arm/mach-hisi/
Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Based on arch/arm/mach-vexpress/platsmp.c, Copyright (C) 2002 ARM Ltd.
23 void hi3xxx_set_cpu_jump(int cpu, void *jump_addr) in hi3xxx_set_cpu_jump() argument
25 cpu = cpu_logical_map(cpu); in hi3xxx_set_cpu_jump()
26 if (!cpu || !ctrl_base) in hi3xxx_set_cpu_jump()
28 writel_relaxed(__pa_symbol(jump_addr), ctrl_base + ((cpu - 1) << 2)); in hi3xxx_set_cpu_jump()
31 int hi3xxx_get_cpu_jump(int cpu) in hi3xxx_get_cpu_jump() argument
33 cpu = cpu_logical_map(cpu); in hi3xxx_get_cpu_jump()
34 if (!cpu || !ctrl_base) in hi3xxx_get_cpu_jump()
36 return readl_relaxed(ctrl_base + ((cpu - 1) << 2)); in hi3xxx_get_cpu_jump()
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/linux-6.14.4/block/
Dblk-mq-cpumap.c1 // SPDX-License-Identifier: GPL-2.0
3 * CPU <-> hardware queue mapping helpers
5 * Copyright (C) 2013-2014 Jens Axboe
12 #include <linux/cpu.h>
17 #include "blk-mq.h"
22 unsigned int queue, cpu; in blk_mq_map_queues() local
24 masks = group_cpus_evenly(qmap->nr_queues); in blk_mq_map_queues()
26 for_each_possible_cpu(cpu) in blk_mq_map_queues()
27 qmap->mq_map[cpu] = qmap->queue_offset; in blk_mq_map_queues()
31 for (queue = 0; queue < qmap->nr_queues; queue++) { in blk_mq_map_queues()
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/linux-6.14.4/arch/s390/mm/
Dmaccess.c1 // SPDX-License-Identifier: GPL-2.0
3 * Access kernel memory without faulting -- s390 specific implementation.
14 #include <linux/cpu.h>
17 #include <asm/asm-extable.h>
30 unsigned long aligned, offset, count; in s390_kernel_write_odd() local
34 offset = (unsigned long) dst & 7UL; in s390_kernel_write_odd()
35 size = min(8UL - offset, size); in s390_kernel_write_odd()
36 count = size - 1; in s390_kernel_write_odd()
46 : "a" (&tmp), "a" (&tmp[offset]), "a" (src) in s390_kernel_write_odd()
52 * __s390_kernel_write - write to kernel memory bypassing DAT
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/linux-6.14.4/arch/x86/platform/uv/
Duv_nmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (C) 2007-2017 Silicon Graphics, Inc. All rights reserved.
10 #include <linux/cpu.h>
37 * Handle system-wide NMI events generated by the global 'power nmi' command.
39 * Basic operation is to field the NMI interrupt on each CPU and wait
40 * until all CPU's have arrived into the nmi handler. If some CPU's do not
50 * second (~4M/s for 1024 CPU threads). Our secondary NMI handler is
66 /* Non-zero indicates newer SMM NMI handler present */
83 #define PCH_PCR_GPIO_ADDRESS(offset) (int *)((u64)(pch_base) | (u64)(offset)) argument
91 static atomic_t uv_nmi_cpu = ATOMIC_INIT(-1);
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/linux-6.14.4/tools/perf/arch/arm/util/
Dcs-etm.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/coresight-pmu.h>
18 #include "cs-etm.h"
29 #include "../../../util/cs-etm.h"
71 static bool cs_etm_is_ete(struct perf_pmu *cs_etm_pmu, struct perf_cpu cpu);
72 static int cs_etm_get_ro(struct perf_pmu *pmu, struct perf_cpu cpu, const char *path, __u64 *val);
73 static bool cs_etm_pmu_path_exists(struct perf_pmu *pmu, struct perf_cpu cpu, const char *path);
76 struct perf_cpu cpu) in cs_etm_get_version() argument
78 if (cs_etm_is_ete(cs_etm_pmu, cpu)) in cs_etm_get_version()
80 else if (cs_etm_pmu_path_exists(cs_etm_pmu, cpu, metadata_etmv4_ro[CS_ETMV4_TRCIDR0])) in cs_etm_get_version()
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/linux-6.14.4/drivers/media/pci/tw68/
Dtw68-risc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * acknowledged. Full credit goes to them - any problems within this code
25 * @sglist: pointer to "scatter-gather list" of buffer pointers
26 * @offset: offset to target memory buffer
27 * @sync_line: 0 -> no sync, 1 -> odd sync, 2 -> even sync
34 unsigned int offset, u32 sync_line, in tw68_risc_field() argument
57 while (offset && offset >= sg_dma_len(sg)) { in tw68_risc_field()
58 offset -= sg_dma_len(sg); in tw68_risc_field()
61 if (bpl <= sg_dma_len(sg) - offset) { in tw68_risc_field()
64 /* (offset<<12) |*/ bpl); in tw68_risc_field()
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/linux-6.14.4/include/linux/
Drelay.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2002, 2003 - Tom Zanussi ([email protected]), IBM Corp
6 * Copyright (C) 1999, 2000, 2001, 2002 - Karim Yaghmour ([email protected])
32 * Per-cpu relay channel buffer
37 void *data; /* start of current sub-buffer */
38 size_t offset; /* current offset into sub-buffer */ member
39 size_t subbufs_produced; /* count of sub-buffers produced */
40 size_t subbufs_consumed; /* count of sub-buffers consumed */
49 size_t *padding; /* padding counts per sub-buffer */
53 unsigned int cpu; /* this buf's cpu */ member
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/linux-6.14.4/tools/power/x86/turbostat/
Dturbostat.83 turbostat \- Report processor frequency and idle statistics
12 .RB [ "\--interval seconds" ]
15 idle power-state statistics, temperature and power on X86 processors.
19 in one-shot upon its completion.
22 The 5-second interval can be changed using the --interval option.
26 Options can be specified with a single or double '-', and only as much of the option
27 name as necessary to disambiguate it from others is necessary. Note that options are case-sensitiv…
29 \fB--add attributes\fP add column with counter having specified 'attributes'. The 'location' attri…
32 msrDDD is a decimal offset, eg. msr16
33 msr0xXXX is a hex offset, eg. msr0x10
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/linux-6.14.4/drivers/virt/coco/arm-cca-guest/
Darm-cca-guest.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/arm-smccc.h>
18 * struct arm_cca_token_info - a descriptor for the token buffer.
22 * @offset: Offset within granule to start of buffer in bytes
29 unsigned long offset; member
39 info->result = rsi_attestation_token_init(info->challenge, in arm_cca_attestation_init()
40 info->challenge_size); in arm_cca_attestation_init()
44 * arm_cca_attestation_continue - Retrieve the attestation token data.
50 * token retrieval operation must be requested on the same CPU on which the
52 * This helper function is therefore scheduled on the same CPU multiple
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/linux-6.14.4/arch/mips/boot/dts/mti/
Dsead3.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/mips-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 compatible = "mti,sead-3";
14 model = "MIPS SEAD-3";
17 stdout-path = "serial1:115200";
26 cpu@0 {
36 cpu_intc: interrupt-controller {
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/linux-6.14.4/arch/x86/kernel/cpu/mce/
Damd.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * (c) 2005-2016 Advanced Micro Devices, Inc.
5 * Written by Jacob Shin - AMD, Inc.
17 #include <linux/cpu.h>
52 /* Threshold LVT offset is at MSR0xC0000410[15:12] */
131 enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank) in smca_get_bank_type() argument
138 b = &per_cpu(smca_banks, cpu)[bank]; in smca_get_bank_type()
139 if (!b->hwid) in smca_get_bank_type()
142 return b->hwid->bank_type; in smca_get_bank_type()
212 * So to define a unique name for each bank, we use a temp c-string to append
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