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/linux-6.14.4/Documentation/devicetree/bindings/mtd/
Dqcom,nandc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <[email protected]>
15 - qcom,ipq806x-nand
16 - qcom,ipq4019-nand
17 - qcom,ipq6018-nand
18 - qcom,ipq8074-nand
19 - qcom,sdx55-nand
26 - description: Core Clock
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/linux-6.14.4/drivers/dma/qcom/
Dqcom_adm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
10 #include <linux/dma-mapping.h>
27 #include "../virt-dma.h"
29 /* ADM registers - calculated from channel number and security domain */
48 #define ADM_CRCI_CTL(crci, ee) (0x400 + (crci) * ADM_CRCI_MULTI + \ argument
71 /* CRCI CTL */
99 #define ADM_MAX_XFER (SZ_64K - 1)
100 #define ADM_MAX_ROWS (SZ_64K - 1)
104 u32 cmd; member
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/linux-6.14.4/include/linux/mtd/
Dnand-qpic-common.h1 /* SPDX-License-Identifier: GPL-2.0 */
196 #define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg))
199 #define nandc_reg_phys(chip, offset) ((chip)->base_phys + (offset))
203 ((chip)->reg_read_dma + \
204 ((u8 *)(vaddr) - (u8 *)(chip)->reg_read_buf))
233 * @bam_ce - the array of BAM command elements
234 * @cmd_sgl - sgl for NAND BAM command pipe
235 * @data_sgl - sgl for NAND BAM consumer/producer pipe
236 * @last_data_desc - last DMA desc in data channel (tx/rx).
237 * @last_cmd_desc - last DMA desc in command channel.
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/linux-6.14.4/drivers/mtd/nand/
Dqpic_common.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
16 #include <linux/mtd/nand-qpic-common.h>
19 * qcom_free_bam_transaction() - Frees the BAM transaction memory
26 struct bam_transaction *bam_txn = nandc->bam_txn; in qcom_free_bam_transaction()
33 * qcom_alloc_bam_transaction() - allocate BAM transaction
43 unsigned int num_cw = nandc->max_cwperpage; in qcom_alloc_bam_transaction()
48 ((sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS) + in qcom_alloc_bam_transaction()
49 (sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL) + in qcom_alloc_bam_transaction()
50 (sizeof(*bam_txn->data_sgl) * QPIC_PER_CW_DATA_SGL)); in qcom_alloc_bam_transaction()
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/linux-6.14.4/drivers/mtd/nand/raw/
Dqcom_nandc.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
18 #include <linux/mtd/nand-qpic-common.h>
42 * @cmd_reg: CMD register value
82 * ecc/non-ecc mode for the current nand flash
132 ((u8 *)chip->controller - sizeof(struct qcom_nand_controller)); in get_qcom_nand_controller()
137 return ioread32(nandc->base + offset); in nandc_read()
143 iowrite32(val, nandc->base + offset); in nandc_write()
149 return cw == (ecc->steps - 1); in qcom_nandc_is_last_cw()
153 * nandc_set_read_loc_first() - to set read location first register
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/linux-6.14.4/arch/arm/boot/dts/qcom/
Dqcom-ipq8064.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
8 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
11 #include <dt-bindings/soc/qcom,gsbi.h>
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