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/linux-6.14.4/Documentation/devicetree/bindings/clock/
Dxgene.txt1 Device Tree Clock bindings for APM X-Gene
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
11 "apm,xgene-pmd-clock" - for a X-Gene PMD clock
12 "apm,xgene-device-clock" - for a X-Gene device clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
[all …]
Dmoxa,moxart-clock.txt1 Device Tree Clock bindings for arch-moxart
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
7 MOXA ART SoCs allow to determine PLL output and APB frequencies
14 - compatible : Must be "moxa,moxart-pll-clock"
15 - #clock-cells : Should be 0
16 - reg : Should contain registers location and length
17 - clocks : Should contain phandle + clock-specifier for the parent clock
20 - clock-output-names : Should contain clock name
26 - compatible : Must be "moxa,moxart-apb-clock"
[all …]
Dlpc1850-cgu.txt1 * NXP LPC1850 Clock Generation Unit (CGU)
4 peripheral blocks of the LPC18xx. Each independent clock is called
5 a base clock and itself is one of the inputs to the two Clock
9 The CGU selects the inputs to the clock generators from multiple
10 clock sources, controls the clock generation, and routes the outputs
11 of the clock generators through the clock source bus to the output
12 stages. Each output stage provides an independent clock source and
15 - Above text taken from NXP LPC1850 User Manual.
18 This binding uses the common clock binding:
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
[all …]
Dfixed-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple fixed-rate clock sources
10 - Michael Turquette <[email protected]>
11 - Stephen Boyd <[email protected]>
16 - description:
17 Preferred name is 'clock-<freq>' with <freq> being the output
18 frequency as defined in the 'clock-frequency' property.
[all …]
Dmaxim,max9485.txt1 Devicetree bindings for Maxim MAX9485 Programmable Audio Clock Generator
5 - MAX9485_MCLKOUT: A gated, buffered output of the input clock of 27 MHz
6 - MAX9485_CLKOUT: A PLL that can be configured to 16 different discrete
8 - MAX9485_CLKOUT[1,2]: Two gated outputs for MAX9485_CLKOUT
14 - compatible: "maxim,max9485"
15 - clocks: Input clock, must provide 27.000 MHz
16 - clock-names: Must be set to "xclk"
17 - #clock-cells: From common clock binding; shall be set to 1
20 - reset-gpios: GPIO descriptor connected to the #RESET input pin
21 - vdd-supply: A regulator node for Vdd
[all …]
Dfixed-factor-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-factor-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple fixed factor rate clock sources
10 - Michael Turquette <[email protected]>
11 - Stephen Boyd <[email protected]>
16 - description:
17 If the frequency is fixed, the preferred name is 'clock-<freq>' with
18 <freq> being the output frequency.
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/display/
Dallwinner,sun8i-r40-tcon-top.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-r40-tcon-top.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <[email protected]>
11 - Maxime Ripard <[email protected]>
16 TCON for HDMI, muxes LCD and TV encoder GPIO output, selects TV
17 encoder clock source and contains additional TV TCON and DSI gates.
22 / [0] TCON-LCD0
25 \ / [1] TCON-LCD1 - LCD1/LVDS1
[all …]
/linux-6.14.4/drivers/clk/at91/
Ddt-compat.c1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
33 const char *name = np->name; in of_sama5d2_clk_audio_pll_frac_setup() local
46 hw = at91_clk_register_audio_pll_frac(regmap, name, parent_name); in of_sama5d2_clk_audio_pll_frac_setup()
53 "atmel,sama5d2-clk-audio-pll-frac",
59 const char *name = np->name; in of_sama5d2_clk_audio_pll_pad_setup() local
72 hw = at91_clk_register_audio_pll_pad(regmap, name, parent_name); in of_sama5d2_clk_audio_pll_pad_setup()
79 "atmel,sama5d2-clk-audio-pll-pad",
85 const char *name = np->name; in of_sama5d2_clk_audio_pll_pmc_setup() local
98 hw = at91_clk_register_audio_pll_pmc(regmap, name, parent_name); in of_sama5d2_clk_audio_pll_pmc_setup()
[all …]
/linux-6.14.4/drivers/clk/ti/
Dadpll.c1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <linux/clk-provider.h>
179 const char *name; in ti_adpll_clk_get_name() local
183 err = of_property_read_string_index(d->np, in ti_adpll_clk_get_name()
184 "clock-output-names", in ti_adpll_clk_get_name()
186 &name); in ti_adpll_clk_get_name()
190 name = devm_kasprintf(d->dev, GFP_KERNEL, "%08lx.adpll.%s", in ti_adpll_clk_get_name()
191 d->pa, postfix); in ti_adpll_clk_get_name()
194 return name; in ti_adpll_clk_get_name()
199 static int ti_adpll_setup_clock(struct ti_adpll_data *d, struct clk *clock, in ti_adpll_setup_clock() argument
[all …]
Dclk.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI clock support
7 * Tero Kristo <t-[email protected]>
12 #include <linux/clk-provider.h>
25 #include "clock.h"
45 struct clk_iomap *io = clk_memmaps[reg->index]; in clk_memmap_writel()
47 if (reg->ptr) in clk_memmap_writel()
48 writel_relaxed(val, reg->ptr); in clk_memmap_writel()
49 else if (io->regmap) in clk_memmap_writel()
50 regmap_write(io->regmap, reg->offset, val); in clk_memmap_writel()
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/mfd/
Dx-powers,ac100.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mfd/x-powers,ac100.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: X-Powers AC100
10 - Chen-Yu Tsai <[email protected]>
14 const: x-powers,ac100
23 "#clock-cells":
27 const: x-powers,ac100-codec
32 clock-output-names:
[all …]
Drockchip,rk805.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chris Zhong <zyw@rock-chips.com>
11 - Zhang Qing <zhangqing@rock-chips.com>
20 - rockchip,rk805
28 '#clock-cells':
30 See <dt-bindings/clock/rockchip,rk808.h> for clock IDs.
34 clock-output-names:
36 From common clock binding to override the default output clock name.
[all …]
Drockchip,rk817.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chris Zhong <zyw@rock-chips.com>
11 - Zhang Qing <zhangqing@rock-chips.com>
21 - rockchip,rk809
22 - rockchip,rk817
30 '#clock-cells':
32 See <dt-bindings/clock/rockchip,rk808.h> for clock IDs.
39 clock-names:
[all …]
/linux-6.14.4/drivers/clk/qcom/
Dipq-cmn-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * CMN PLL block expects the reference clock from on-board Wi-Fi block,
8 * and supplies fixed rate clocks as output to the networking hardware
13 * On the IPQ9574 SoC, there are three clocks with 50 MHZ and one clock
14 * with 25 MHZ which are output from the CMN PLL to Ethernet PHY (or switch),
15 * and one clock with 353 MHZ to PPE. The other fixed rate output clocks
16 * are supplied to GCC (24 MHZ as XO and 32 KHZ as sleep clock), and to PCS
19 * +---------+
21 * +--+---+--+
24 * +-------+---+------+
[all …]
/linux-6.14.4/Documentation/ABI/testing/
Dsysfs-bus-counter3 Contact: linux-[email protected]
11 Contact: linux-[email protected]
13 Selects the external clock pin for phase counting mode of
16 MTCLKA-MTCLKB:
18 phase clock.
20 MTCLKC-MTCLKD:
22 phase clock.
26 Contact: linux-[email protected]
33 Contact: linux-[email protected]
39 Contact: linux-[email protected]
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/clock/ti/davinci/
Dpll.txt5 an multiplexers for various clock signals.
8 - compatible: shall be one of:
9 - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
10 - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
11 - reg: physical base address and size of the controller's register area.
12 - clocks: phandles corresponding to the clock names
13 - clock-names: names of the clock sources - depends on compatible string
14 - for "ti,da850-pll0", shall be "clksrc", "extclksrc"
15 - for "ti,da850-pll1", shall be "clksrc"
18 - ti,clkmode-square-wave: Indicates that the board is supplying a square
[all …]
/linux-6.14.4/tools/perf/tests/shell/
Ddaemon.sh3 # SPDX-License-Identifier: GPL-2.0
8 local name=$2
10 local output=$4
25 if [ "${name}" != "${line_name}" ]; then
26 echo "FAILED: wrong name"
35 if [ "${output}" != "${line_output}" ]; then
36 echo "FAILED: wrong output"
54 local name=$2
57 local output=$5
77 if [ "${name}" != "${line_name}" ]; then
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/leds/
Dleds-lp55xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/leds-lp55xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacek Anaszewski <[email protected]>
11 - Pavel Machek <[email protected]>
27 - national,lp5521
28 - national,lp5523
29 - ti,lp55231
30 - ti,lp5562
[all …]
/linux-6.14.4/drivers/comedi/drivers/
Damplc_dio200.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Copyright (C) 2005-2013 MEV Ltd. <https://www.mev.co.uk/>
9 * COMEDI - Linux Control and Measurement Device Interface
24 * [0] - I/O port base address
25 * [1] - IRQ (optional, but commands won't work without it)
32 * ------------- ------------- -------------
34 * 0 PPI-X PPI-X PPI-X
35 * 1 CTR-Y1 PPI-Y PPI-Y
36 * 2 CTR-Y2 CTR-Z1* CTR-Z1
37 * 3 CTR-Z1 INTERRUPT* CTR-Z2
[all …]
Damplc_dio200_pci.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 2005-2013 MEV Ltd. <https://www.mev.co.uk/>
8 * COMEDI - Linux Control and Measurement Device Interface
30 * ------------- ------------- -------------
32 * 0 PPI-X PPI-X PPI-X
33 * 1 PPI-Y UNUSED UNUSED
34 * 2 CTR-Z1 PPI-Y UNUSED
35 * 3 CTR-Z2 UNUSED UNUSED
36 * 4 INTERRUPT CTR-Z1 CTR-Z1
37 * 5 CTR-Z2 CTR-Z2
[all …]
/linux-6.14.4/arch/arm/boot/dts/rockchip/
Drk3288-firefly-reload-core.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/input/input.h>
16 ext_gmac: external-gmac-clock {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
19 clock-frequency = <125000000>;
20 clock-output-names = "ext_gmac";
24 vcc_flash: regulator-flash {
25 compatible = "regulator-fixed";
26 regulator-name = "vcc_flash";
[all …]
Drk3288-r89.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/pwm/pwm.h>
20 ext_gmac: external-gmac-clock {
21 compatible = "fixed-clock";
22 clock-frequency = <125000000>;
23 clock-output-names = "ext_gmac";
24 #clock-cells = <0>;
27 gpio-keys {
[all …]
Drk3288-miqi.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/input/input.h>
15 stdout-path = "serial2:115200n8";
23 ext_gmac: external-gmac-clock {
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <125000000>;
27 clock-output-names = "ext_gmac";
31 compatible = "gpio-leds";
[all …]
/linux-6.14.4/drivers/clk/st/
Dclkgen-fsyn.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/clk-provider.h>
20 * Maximum input clock to the PLL before we divide it down by 2
70 const char *name; member
82 unsigned long output, struct stm_fs *fs);
129 { .name = "clk-s-c0-fs0-ch0", },
130 { .name = "clk-s-c0-fs0-ch1", },
131 { .name = "clk-s-c0-fs0-ch2", },
132 { .name = "clk-s-c0-fs0-ch3", },
186 { .name = "clk-s-d0-fs0-ch0", },
[all …]
/linux-6.14.4/Documentation/sound/cards/
Dhdspm.rst2 Software Interface ALSA-DSP MADI Driver
5 (translated from German, so no good English ;-),
7 2004 - winfried ritsch
11 the Controls and startup-options are ALSA-Standard and only the
19 ------------------
21 * number of channels -- depends on transmission mode
29 * Single Speed -- 1..64 channels
37 * Double Speed -- 1..32 channels
40 Note: Choosing the 56-channel mode for
41 transmission/receive-mode , only 28 are transmitted/received
[all …]

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