| /linux-6.14.4/Documentation/devicetree/bindings/iio/adc/ |
| D | st,stm32-dfsdm-adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-dfsdm-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabrice Gasnier <[email protected]>
11 - Olivier Moysan <[email protected]>
14 STM32 DFSDM ADC is a sigma delta analog-to-digital converter dedicated to
17 - Sigma delta modulators (motor control, metering...)
18 - PDM microphones (audio digital microphone)
28 - st,stm32h7-dfsdm
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| /linux-6.14.4/Documentation/devicetree/bindings/soc/fsl/cpm_qe/ |
| D | fsl,cpm1-tsa.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC CPM Time-slot assigner (TSA) controller
10 - Herve Codina <[email protected]>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc885-tsa
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| D | fsl,qe-tsa.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC QE Time-slot assigner (TSA) controller
10 - Herve Codina <[email protected]>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc8321-tsa
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| /linux-6.14.4/Documentation/devicetree/bindings/display/panel/ |
| D | panel-timing.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-timing.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <[email protected]>
11 - Sam Ravnborg <[email protected]>
20 +-------+----------+-------------------------------------+----------+
24 +-------+----------+-------------------------------------+----------+
28 +-------+----------#######################################----------+
33 |<----->|<-------->#<-------+--------------------------->#<-------->|
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| /linux-6.14.4/Documentation/devicetree/bindings/net/ |
| D | lantiq,pef2256.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Herve Codina <[email protected]>
20 - const: lantiq,pef2256
27 - description: Master Clock
28 - description: System Clock Receive
29 - description: System Clock Transmit
31 clock-names:
33 - const: mclk
[all …]
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| /linux-6.14.4/sound/soc/ti/ |
| D | davinci-i2s.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 * based on davinci-mcasp.c DT support
30 #include "edma-pcm.h"
31 #include "davinci-i2s.h"
33 #define DRV_NAME "davinci-i2s"
38 * - This driver supports the "Audio Serial Port" (ASP),
41 * - But it labels it a "Multi-channel Buffered Serial Port"
43 * backward-compatible, possibly explaining that confusion.
45 * - OMAP chips have a controller called McBSP, which is
48 * - Newer DaVinci chips have a controller called McASP,
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| /linux-6.14.4/Documentation/devicetree/bindings/sound/ |
| D | cirrus,cs42l43.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - [email protected]
21 - $ref: dai-common.yaml#
26 - cirrus,cs42l43
31 vdd-p-supply:
35 vdd-a-supply:
39 vdd-d-supply:
43 vdd-io-supply:
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| D | microchip,sama7g5-pdmc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/microchip,sama7g5-pdmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Codrin Ciubotariu <[email protected]>
17 - $ref: dai-common.yaml#
21 const: microchip,sama7g5-pdmc
26 "#sound-dai-cells":
34 - description: Peripheral Bus Clock
35 - description: Generic Clock
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| /linux-6.14.4/Documentation/sound/soc/ |
| D | dai.rst | 15 The bit clock (BCLK) is always driven by the CODEC (usually 12.288MHz) and the
27 Rx lines are used for audio transmission, while the bit clock (BCLK) and
28 left/right clock (LRC) synchronise the link. I2S is flexible in that either the
29 controller or CODEC can drive (master) the BCLK and LRC clock lines. Bit clock
30 usually varies depending on the sample rate and the master system clock
35 I2S has several different operating modes:-
38 MSB is transmitted on the falling edge of the first BCLK after LRC
51 flexible protocol. It has bit clock (BCLK) and sync (SYNC) lines that are used
53 receive the audio data. Bit clock usually varies depending on sample rate
58 Common PCM operating modes:-
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| /linux-6.14.4/drivers/media/dvb-frontends/ |
| D | m88ds3103.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
19 * enum m88ds3103_ts_mode - TS connection mode
34 * @M88DS3103_CLOCK_OUT_DISABLED: Clock output is disabled
35 * @M88DS3103_CLOCK_OUT_ENABLED: Clock output is enabled with crystal
36 * clock.
37 * @M88DS3103_CLOCK_OUT_ENABLED_DIV2: Clock output is enabled with half
38 * crystal clock.
47 * struct m88ds3103_platform_data - Platform data for the m88ds3103 driver
48 * @clk: Clock frequency.
51 * @ts_clk: TS clock (KHz).
[all …]
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| /linux-6.14.4/Documentation/devicetree/bindings/net/dsa/ |
| D | qca8k.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - John Crispin <[email protected]>
13 If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
16 ID. To declare the internal mdio-bus configuration, declare an MDIO node in
18 PHY it is connected to. In this config, an internal mdio-bus is registered and
20 mdio-bus configurations are not supported by the hardware.
27 - enum:
28 - qca,qca8327
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| /linux-6.14.4/drivers/staging/greybus/ |
| D | audio_apbridgea.h | 1 /* SPDX-License-Identifier: BSD-3-Clause */
3 * Copyright (c) 2015-2016 Google Inc.
8 * we can predefine several low-level attributes of the communication
11 * - there are two channels (i.e., stereo)
12 * - the low-level protocol is I2S as defined by Philips/NXP
13 * - the DSP on the MSM8994 is the clock master for MCLK, BCLK, and WCLK
14 * - WCLK changes on the falling edge of BCLK
15 * - WCLK low for left channel; high for right channel
16 * - TX data is sent on the falling edge of BCLK
17 * - RX data is received/latched on the rising edge of BCLK
|
| /linux-6.14.4/Documentation/userspace-api/gpio/ |
| D | gpio-lineevent-data-read.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 gpio-v2-line-event-read.rst.
16 GPIO_LINEEVENT_DATA_READ - Read edge detection events from a line event.
28 :c:type:`request.fd<gpioevent_request>` by gpio-get-lineevent-ioctl.rst.
40 Read edge detection events for a line from a line event.
42 Edge detection must be enabled for the input line using either
44 both. Edge events are then generated whenever edge interrupts are detected on
48 to active transition is a rising edge. If ``GPIOHANDLE_REQUEST_ACTIVE_LOW`` is
50 ``GPIOEVENT_REQUEST_RISING_EDGE`` then corresponds to a falling physical edge.
52 The kernel captures and timestamps edge events as close as possible to their
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| /linux-6.14.4/drivers/staging/sm750fb/ |
| D | ddk750_sii164.c | 1 // SPDX-License-Identifier: GPL-2.0
79 * edge_select - Edge Select:
80 * 0 = Input data is falling edge latched (falling
81 * edge latched first in dual edge mode)
82 * 1 = Input data is rising edge latched (rising
83 * edge latched first in dual edge mode)
84 * bus_select - Input Bus Select:
85 * 0 = Input data bus is 12-bits wide
86 * 1 = Input data bus is 24-bits wide
87 * dual_edge_clk_select - Dual Edge Clock Select
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| /linux-6.14.4/drivers/atm/ |
| D | nicstarmac.c | 1 // SPDX-License-Identifier: GPL-2.0
27 /* Write Data To EEProm from SI line on rising edge of CLK */
28 /* Read Data From EEProm on falling edge of CLK */
32 #define CLK_HIGH 0x0004 /* Clock high */
33 #define CLK_LOW 0x0000 /* Clock low */
83 /* Clock to read from/write to the eeprom */
112 * This routine will clock the Read_Status_reg function into the X2520
132 /* Done sending instruction - now pull data off of bit 16, MSB first */
133 /* Data clocked out of eeprom on falling edge of clock */
136 for (i = 7, j = 0; i >= 0; i--) {
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| /linux-6.14.4/arch/mips/mti-malta/ |
| D | malta-time.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Setting up the clock on the MIPS boards.
28 #include <asm/mc146818-time.h>
30 #include <asm/mips-cps.h>
32 #include <asm/mips-boards/generic.h>
33 #include <asm/mips-boards/maltaint.h>
54 freq -= freq % (amount*2); in freqround()
75 * Read counters exactly on rising edge of update flag. in estimate_frequencies()
84 /* Wait for falling edge before reading RTC. */ in estimate_frequencies()
88 /* Read counters again exactly on rising edge of update flag. */ in estimate_frequencies()
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| /linux-6.14.4/drivers/pinctrl/ |
| D | pinctrl-at91.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Parallel I/O Controller (PIO) - System peripherals registers.
29 #define PIO_MDER 0x50 /* Multi-driver Enable Register */
30 #define PIO_MDDR 0x54 /* Multi-driver Disable Register */
31 #define PIO_MDSR 0x58 /* Multi-driver Status Register */
32 #define PIO_PUDR 0x60 /* Pull-up Disable Register */
33 #define PIO_PUER 0x64 /* Pull-up Enable Register */
34 #define PIO_PUSR 0x68 /* Pull-up Status Register */
40 #define PIO_IFSCDR 0x80 /* Input Filter Slow Clock Disable Register */
41 #define PIO_IFSCER 0x84 /* Input Filter Slow Clock Enable Register */
[all …]
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| /linux-6.14.4/Documentation/ABI/testing/ |
| D | sysfs-bus-counter | 3 Contact: linux-[email protected]
11 Contact: linux-[email protected]
13 Selects the external clock pin for phase counting mode of
16 MTCLKA-MTCLKB:
18 phase clock.
20 MTCLKC-MTCLKD:
22 phase clock.
26 Contact: linux-[email protected]
33 Contact: linux-[email protected]
39 Contact: linux-[email protected]
[all …]
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| /linux-6.14.4/drivers/gpu/drm/sti/ |
| D | sti_vtg.c | 1 // SPDX-License-Identifier: GPL-2.0
74 #define AWG_DELAY_HD (-9)
75 #define AWG_DELAY_ED (-8)
76 #define AWG_DELAY_SD (-7)
110 *@hsync: sample number falling and rising edge
111 *@vsync_line_top: vertical top field line number falling and rising edge
112 *@vsync_line_bot: vertical bottom field line number falling and rising edge
113 *@vsync_off_top: vertical top field sample number rising and falling edge
114 *@vsync_off_bot: vertical bottom field sample number rising and falling edge
156 writel(1, vtg->regs + VTG_DRST_AUTOC); in vtg_reset()
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| /linux-6.14.4/drivers/gpio/ |
| D | gpio-stp-xway.c | 1 // SPDX-License-Identifier: GPL-2.0-only
50 /* clock source for automatic update */
71 /* Edge configuration bits */
83 u32 edge; /* rising or falling edge triggered shift register */ member
85 u8 groups; /* we can drive 1-3 groups of 8bit each */
95 * xway_stp_get() - gpio_chip->get - get gpios.
105 return (xway_stp_r32(chip->virt, XWAY_STP_CPU0) & BIT(gpio)); in xway_stp_get()
109 * xway_stp_set() - gpio_chip->set - set gpios.
121 chip->shadow |= BIT(gpio); in xway_stp_set()
123 chip->shadow &= ~BIT(gpio); in xway_stp_set()
[all …]
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| /linux-6.14.4/Documentation/devicetree/bindings/watchdog/ |
| D | nuvoton,npcm-wdt.txt | 3 Nuvoton NPCM timer module provides five 24-bit timer counters, and a watchdog.
4 The watchdog supports a pre-timeout interrupt that fires 10ms before the
8 - compatible : "nuvoton,npcm750-wdt" for NPCM750 (Poleg), or
9 "nuvoton,wpcm450-wdt" for WPCM450 (Hermon), or
10 "nuvoton,npcm845-wdt" for NPCM845 (Arbel).
11 - reg : Offset and length of the register set for the device.
12 - interrupts : Contain the timer interrupt with flags for
13 falling edge.
16 - clocks : phandle of timer reference clock.
17 - clock-frequency : The frequency in Hz of the clock that drives the NPCM7xx
[all …]
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| /linux-6.14.4/include/sound/ |
| D | soc-dai.h | 1 /* SPDX-License-Identifier: GPL-2.0
3 * linux/sound/soc-dai.h -- ALSA SoC Layer
5 * Copyright: 2005-2008 Wolfson Microelectronics. PLC.
56 * DAI Clock gating.
61 #define SND_SOC_DAIFMT_CONT (1 << 4) /* continuous clock */
62 #define SND_SOC_DAIFMT_GATED (0 << 4) /* clock is gated */
66 * define GATED -> CONT. GATED will be selected if both are selected.
82 * - "normal" polarity means signal is available at rising edge of BCLK
83 * - "inverted" polarity means signal is available at falling edge of BCLK
86 * - I2S: frame consists of left then right channel data. Left channel starts
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| /linux-6.14.4/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpc5200.txt | 2 ----------------------------
4 (c) 2006-2009 Secret Lab Technologies Ltd
8 ------------------
9 For mpc5200 on-chip devices, the format for each compatible value is
10 <chip>-<device>[-<mode>]. The OS should be able to match a device driver
21 "fsl,mpc5200-<device>".
29 compatible = "fsl,mpc5200b-<device>","fsl,mpc5200-<device>";
34 ie. ethernet on mpc5200: compatible = "fsl,mpc5200-fec";
35 ethernet on mpc5200b: compatible = "fsl,mpc5200b-fec", "fsl,mpc5200-fec";
39 "fsl,mpc5200-psc-i2s", not "fsl,mpc5200-i2s". This convention is chosen to
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| /linux-6.14.4/Documentation/devicetree/bindings/timer/ |
| D | faraday,fttmr010.txt | 8 - compatible : Must be one of
10 "cortina,gemini-timer", "faraday,fttmr010"
11 "moxa,moxart-timer", "faraday,fttmr010"
12 "aspeed,ast2400-timer"
13 "aspeed,ast2500-timer"
14 "aspeed,ast2600-timer"
16 - reg : Should contain registers location and length
17 - interrupts : Should contain the three timer interrupts usually with
18 flags for falling edge
22 - clocks : a clock to provide the tick rate for "faraday,fttmr010"
[all …]
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| /linux-6.14.4/include/media/i2c/ |
| D | tvp7002.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics
6 * Author: Santiago Nunez-Corrales <[email protected]>
19 * struct tvp7002_config - Platform dependent data
20 *@clk_polarity: Clock polarity
21 * 0 - Data clocked out on rising edge of DATACLK signal
22 * 1 - Data clocked out on falling edge of DATACLK signal
24 * 0 - Active low HSYNC output, 1 - Active high HSYNC output
26 * 0 - Active low VSYNC output, 1 - Active high VSYNC output
27 *@fid_polarity: Active-high Field ID polarity.
[all …]
|