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/linux-6.14.4/Documentation/devicetree/bindings/serial/
Dactions,owl-uart.yaml46 clocks = <&cmu CLK_UART0>;
Dsprd-uart.yaml74 clocks = <&clk_ap_apb_gates 9>, <&clk_uart0>, <&ext_26m>;
/linux-6.14.4/include/dt-bindings/clock/
Dexynos5410.h36 #define CLK_UART0 257 macro
Dactions,s500-cmu.h58 #define CLK_UART0 38 macro
Dactions,s700-cmu.h58 #define CLK_UART0 36 macro
Dactions,s900-cmu.h85 #define CLK_UART0 67 macro
Dsophgo,cv1800.h88 #define CLK_UART0 77 macro
Dpistachio-clk.h39 #define CLK_UART0 48 macro
Dexynos5250.h93 #define CLK_UART0 289 macro
Ds5pv210.h161 #define CLK_UART0 143 macro
Dexynos5420.h66 #define CLK_UART0 257 macro
Dexynos4.h150 #define CLK_UART0 312 macro
Dexynos3250.h222 #define CLK_UART0 216 macro
Dsprd,ums512-clk.h139 #define CLK_UART0 11 macro
Dsprd,sc9860-clk.h85 #define CLK_UART0 2 macro
/linux-6.14.4/drivers/clk/actions/
Dowl-s700.c282 static OWL_COMP_DIV(clk_uart0, "uart0", uart_clk_mux_p,
445 &clk_uart0.common,
528 [CLK_UART0] = &clk_uart0.common.hw,
/linux-6.14.4/drivers/clk/hisilicon/
Dclk-hi3519.c58 { HI3519_UART0_CLK, "clk_uart0", "24m",
Dcrg-hi3516cv300.c87 { HI3516CV300_UART0_CLK, "clk_uart0", "uart_mux", CLK_SET_RATE_PARENT,
Dcrg-hi3798cv200.c285 { HISTB_UART0_CLK, "clk_uart0", "75m",
/linux-6.14.4/drivers/clk/sophgo/
Dclk-cv1800.c519 static CV1800_GATE(clk_uart0, clk_uart_parents,
1106 [CLK_UART0] = &clk_uart0.common.hw,
1337 [CLK_UART0] = &clk_uart0.common.hw,
/linux-6.14.4/arch/arm/boot/dts/samsung/
Ds5pv210.dtsi321 clocks = <&clocks CLK_UART0>, <&clocks CLK_UART0>,
/linux-6.14.4/arch/arm64/boot/dts/actions/
Ds700.dtsi119 clocks = <&cmu CLK_UART0>;
Ds900.dtsi125 clocks = <&cmu CLK_UART0>;
/linux-6.14.4/arch/arm64/boot/dts/sprd/
Dwhale2.dtsi78 <&ap_clk CLK_UART0>,
/linux-6.14.4/arch/arm/boot/dts/actions/
Dowl-s500.dtsi136 clocks = <&cmu CLK_UART0>;

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