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Searched +full:clk +full:- +full:freq +full:- +full:optimized (Results 1 – 13 of 13) sorted by relevance

/linux-6.14.4/drivers/opp/
Dti-opp-supply.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/
5 * Dave Gerlach <d-[email protected]>
11 #include <linux/clk.h>
26 * struct ti_opp_supply_optimum_voltage_table - optimized voltage table
28 * @optimized_uv: Optimized voltage from efuse
36 * struct ti_opp_supply_data - OMAP specific opp supply data
37 * @vdd_table: Optimized voltage mapping table
54 * struct ti_opp_supply_of_data - device tree match data
57 * @efuse_voltage_uv: Are the efuse entries in micro-volts? if not, assume
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/linux-6.14.4/Documentation/devicetree/bindings/i2c/
Dsnps,designware-i2c.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/i2c/snps,designware-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jarkko Nikula <[email protected]>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
14 - if:
19 const: mscc,ocelot-i2c
28 - description: Generic Synopsys DesignWare I2C controller
29 const: snps,designware-i2c
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/linux-6.14.4/Documentation/scsi/
Dufs.rst1 .. SPDX-License-Identifier: GPL-2.0
29 embedded and removable flash memory-based storage in mobile
32 on the MIPI M-PHY physical layer standard. UFS uses MIPI M-PHY as the
37 * Optimized performance:
41 - Support for Gear1 is mandatory (rate A: 1248Mbps, rate B: 1457.6Mbps)
42 - Support for Gear2 is optional (rate A: 2496Mbps, rate B: 2915.2Mbps)
46 - Gear3 (rate A: 4992Mbps, rate B: 5830.4Mbps)
56 SAM-5 architectural model.
61 ---------------------
68 UFS supports a subset of SCSI commands defined by SPC-4 and SBC-3.
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/linux-6.14.4/arch/microblaze/boot/dts/
Dsystem.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * (C) Copyright 2007-2008 Xilinx, Inc.
6 * (C) Copyright 2007-2009 Michal Simek
13 * XPS project directory: Xilinx-ML505-ll_temac-sgdma-MMU-FDT-edk101
16 /dts-v1/;
18 #address-cells = <1>;
19 #size-cells = <1>;
32 stdout-path = "/plb@0/serial@84000000";
35 #address-cells = <1>;
37 #size-cells = <0>;
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/linux-6.14.4/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/
Ddml2_internal_shared_types.h1 // SPDX-License-Identifier: MIT
311 // Meta-data for implicit SVP generation, indexed by stream index
314 // Meta-data for FAMS2
399 * Outputs (also Input the clk freq are also from programming struct)
603 …NO_DRR_STRATEGY_MASK (((1 << (dml2_pstate_method_reserved_fw - dml2_pstate_method_na + 1)) - 1) <<…
604 …Y_MASK (((1 << (dml2_pstate_method_reserved_fw_drr_var - dml2_pstate_method_fw_vactive_drr + 1)) -…
605 …SK (((1 << (dml2_pstate_method_reserved_fw_drr_clamped - dml2_pstate_method_fw_vactive_drr + 1)) -…
606 …ATEGY_MASK (((1 << (dml2_pstate_method_reserved_fw_drr_var - dml2_pstate_method_fw_drr + 1)) - 1) …
607 …ATEGY_MASK (((1 << (dml2_pstate_method_reserved_fw_drr_var - dml2_pstate_method_fw_svp + 1)) - 1) …
890 …on_optimize_function_params *params); // Function which produces a more optimized display configur…
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/linux-6.14.4/drivers/i2c/busses/
Di2c-designware-common.c1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include <linux/clk.h>
35 #include "i2c-designware-core.h"
65 "incorrect slave-transmitter mode configuration",
72 *val = readl(dev->base + reg); in dw_reg_read()
81 writel(val, dev->base + reg); in dw_reg_write()
90 *val = swab32(readl(dev->base + reg)); in dw_reg_read_swab()
99 writel(swab32(val), dev->base + reg); in dw_reg_write_swab()
108 *val = readw(dev->base + reg) | in dw_reg_read_word()
109 (readw(dev->base + reg + 2) << 16); in dw_reg_read_word()
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/linux-6.14.4/drivers/media/dvb-frontends/
Dstv090x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
52 ((temp_dev->internal->i2c_adap != i2c_adap) || in find_dev()
53 (temp_dev->internal->i2c_addr != i2c_addr))) { in find_dev()
55 temp_dev = temp_dev->next_dev; in find_dev()
65 struct stv090x_dev *del_dev = find_dev(internal->i2c_adap, in remove_dev()
66 internal->i2c_addr); in remove_dev()
70 stv090x_first_dev = del_dev->next_dev; in remove_dev()
72 while (prev_dev->next_dev != del_dev) in remove_dev()
73 prev_dev = prev_dev->next_dev; in remove_dev()
75 prev_dev->next_dev = del_dev->next_dev; in remove_dev()
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/linux-6.14.4/sound/pci/
Dazt3328.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* azt3328.c - driver for Aztech AZF3328 based soundcards (e.g. PCI168).
3 * Copyright (C) 2002, 2005 - 2011 by Andreas Mohr <andi AT lisas.de>
7 * found in a Fujitsu-Siemens PC ("Cordant", aluminum case).
13 * Keywords: Windows XP Vista 168nt4-125.zip 168win95-125.zip PCI 168 download
17 * despite the high level of Internet ignorance - as usual :-P -
18 * about very good support for this card - on Linux!)
25 * in the first place >:-P}),
34 * for compatibility reasons) from Azfin (joint-venture of Aztech and Fincitec,
36 * Fincitec-related company ARSmikro) has the following features:
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/linux-6.14.4/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/
Dphy_cmn.c1 // SPDX-License-Identifier: ISC
30 /* basic mux operation - can be optimized on several architectures */
33 /* modulo inc/dec - assumes x E [0, bound - 1] */
34 #define MODINC(x, bound) MUX((x) == (bound) - 1, 0, (x) + 1)
37 #define MODDEC_POW2(x, bound) (((x) - 1) & ((bound) - 1))
38 #define MODINC_POW2(x, bound) (((x) + 1) & ((bound) - 1))
42 u16 freq; member
121 wlapi_bmac_ucode_wake_override_phyreg_set(pi->sh->physhim); in wlc_phyreg_enter()
127 wlapi_bmac_ucode_wake_override_phyreg_clear(pi->sh->physhim); in wlc_phyreg_exit()
133 wlapi_bmac_mctrl(pi->sh->physhim, MCTL_LOCK_RADIO, MCTL_LOCK_RADIO); in wlc_radioreg_enter()
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/linux-6.14.4/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
Ddcn32_hwseq.c59 hws->ctx
61 hws->regs->reg
63 dc->ctx->logger
67 hws->shifts->field_name, hws->masks->field_name
77 struct dc *dc = hws->ctx->dc; in dcn32_dsc_pg_control()
79 if (dc->debug.disable_dsc_power_gate) in dcn32_dsc_pg_control()
82 if (!dc->debug.enable_double_buffered_dsc_pg_support) in dcn32_dsc_pg_control()
168 if (hws->ctx->dc->debug.disable_hubp_power_gate) in dcn32_hubp_pg_control()
201 /* First, check no-memory-request case */ in dcn32_check_no_memory_request_for_cab()
202 for (i = 0; i < dc->current_state->stream_count; i++) { in dcn32_check_no_memory_request_for_cab()
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/linux-6.14.4/drivers/mmc/host/
Dsdhci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
5 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
9 * - JMicron (hardware and technical support)
19 #include <linux/dma-mapping.h>
33 #include <linux/mmc/slot-gpio.h>
40 pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
43 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
71 SDHCI_DUMP("Wake-up: 0x%08x | Clock: 0x%08x\n", in sdhci_dumpregs()
98 if (host->flags & SDHCI_USE_ADMA) { in sdhci_dumpregs()
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/linux-6.14.4/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
Ddcn401_hwseq.c1 // SPDX-License-Identifier: MIT
41 hws->ctx
43 hws->regs->reg
45 dc->ctx->logger
50 hws->shifts->field_name, hws->masks->field_name
54 struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk; in dcn401_initialize_min_clocks()
56 clocks->dcfclk_deep_sleep_khz = DCN3_2_DCFCLK_DS_INIT_KHZ; in dcn401_initialize_min_clocks()
57 clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000; in dcn401_initialize_min_clocks()
58 clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000; in dcn401_initialize_min_clocks()
59 clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000; in dcn401_initialize_min_clocks()
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/linux-6.14.4/drivers/gpu/drm/amd/display/dmub/inc/
Ddmub_cmd.h143 * Physical framebuffer address location, 64-bit.
255 * @knee_threshold: Current x-position of ACE knee (u0.16).
275 * union dmub_addr - DMUB physical/virtual 64-bit address.
457 * 0x1 (bit 0) - Desync Error flag.
462 * 0x2 (bit 1) - State Transition Error flag.
467 * 0x4 (bit 2) - Crc Error flag
472 * 0x8 (bit 3) - Reserved
477 * 0x10 (bit 4) - Incorrect Coasting vtotal checking --> use debug flag to control DPCD write.
483 * 0x20 (bit 5) - No doubled Refresh Rate.
488 * Reserved bit 6-7
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