Searched full:bitstreams (Results 1 – 19 of 19) sorted by relevance
33 The system controller may retrieve FPGA bitstreams from this flash to37 MSS can write bitstreams to the flash.
3 This simple SPI master controller is built into xtfpga bitstreams and is used
1 Bindings for I2S controller built into xtfpga Xtensa bitstreams.
12 raw uncompressed formats in various compressed video bitstreams format.
68 no support for encoding continuous bitstreams with a symbol size != 8 at98 no support for decoding continuous bitstreams with a symbolsize != 8 at
117 * Display reminder for early engr test or demo chips / FPGA bitstreams
13 Description: Read-only. User can program different PR bitstreams to FPGA
130 * actually seem to be connected for those Malta bitstreams. in get_c0_fdc_int()
248 * Hardware circumvention section. Certain bitstreams in our test-lab250 * bitstreams to function will with this version of our device driver.287 * Bitstreams older than 2013-02-17 have a bug where fatal GFIRs must289 * manufacturer, but also for some old bitstreams we released to our
697 "[%s] masking errors for old bitstreams\n", __func__); in genwqe_card_reset()
279 /* Clock rate varies among FPGA bitstreams; board specific FPGA register in xtavnet_init()
27 * The trans buffer size of FHD and 4K bitstreams are different.
270 "System not secure, can't use encrypted bitstreams\n"); in zynq_fpga_ops_write_init()
200 * bitstreams and a different method of clearing the state.
14 * are different bitstreams for different expansion modules). When no expansion
630 /* finish bitStreams one by one */ in HUF_decompress4X1_usingDTable_internal_body()1346 /* finish bitStreams one by one */ in HUF_decompress4X2_usingDTable_internal_body()1408 /* finish bitStreams one by one */ in HUF_decompress4X2_usingDTable_internal_bmi2_asm()
1214 This simple SPI master controller is built into xtfpga bitstreams
684 /* Add typegroup bits to the key/mask bitstreams */ in vcap_encode_rule_keyset()842 /* Add typegroup bits to the entry bitstreams */ in vcap_encode_rule_actionset()2472 /* Encode the bitstreams to the VCAP cache */ in vcap_mod_rule()
685 * for parsing bitstreams change internal state of VPU in some in cedrus_vp8_setup()