Searched full:aud_pll_div0_lpcg (Results 1 – 5 of 5) sorted by relevance
20 <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>,50 <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>,243 <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>,
129 <&aud_pll_div0_lpcg IMX_LPCG_CLK_4>,456 <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>,595 aud_pll_div0_lpcg: clock-controller@59d20000 { label658 <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>,
37 <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>,
253 assigned-clock-parents = <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>;
248 <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>,