Home
last modified time | relevance | path

Searched +full:am654 +full:- +full:tx +full:- +full:pru (Results 1 – 9 of 9) sorted by relevance

/linux-6.14.4/Documentation/devicetree/bindings/remoteproc/
Dti,pru-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,pru-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI Programmable Realtime Unit (PRU) cores
10 - Suman Anna <s-[email protected]>
13 Each Programmable Real-Time Unit and Industrial Communication Subsystem
14 (PRU-ICSS or PRUSS) has two 32-bit load/store RISC CPU cores called
15 Programmable Real-Time Units (PRUs), each represented by a node. Each PRU
17 use the Data RAMs present within the PRU-ICSS for code execution.
[all …]
/linux-6.14.4/arch/arm64/boot/dts/ti/
Dk3-am65-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy-am654-serdes.h>
11 compatible = "mmio-sram";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 atf-sram@0 {
21 sysfw-sram@f0000 {
25 l3cache-sram@100000 {
30 gic500: interrupt-controller@1800000 {
[all …]
Dk3-am64-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
[all …]
Dk3-j721e-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/phy/phy-ti.h>
9 #include <dt-bindings/mux/mux.h>
11 #include "k3-serdes.h"
14 cmn_refclk: clock-cmnrefclk {
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <0>;
[all …]
Dk3-am65-iot2050-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) Siemens AG, 2018-2024
12 #include <dt-bindings/leds/common.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/net/ti-dp83867.h>
36 stdout-path = "serial3:115200n8";
39 reserved-memory {
40 #address-cells = <2>;
41 #size-cells = <2>;
44 secure_ddr: secure-ddr@9e800000 {
[all …]
/linux-6.14.4/drivers/remoteproc/
Dpru_rproc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PRU-ICSS remoteproc driver for various TI SoCs
5 * Copyright (C) 2014-2022 Texas Instruments Incorporated - https://www.ti.com/
8 * Suman Anna <s-[email protected]>
11 * Puranjay Mohan <p-[email protected]>
41 /* CTRL register bit-fields */
53 /* PRU/RTU/Tx_PRU Core IRAM address masks */
62 /* PRU device addresses for various type of PRU RAMs */
71 * enum pru_iomem - PRU core memory/register range identifiers
73 * @PRU_IOMEM_IRAM: PRU Instruction RAM range
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/net/
Dti,icssg-prueth.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,icssg-prueth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Md Danish Anwar <[email protected]>
13 Ethernet based on the Programmable Real-Time Unit and Industrial
19 - ti,am642-icssg-prueth # for AM64x SoC family
20 - ti,am654-icssg-prueth # for AM65x SoC family
21 - ti,am654-sr1-icssg-prueth # for AM65x SoC family, SR1.0
32 dma-names:
[all …]
/linux-6.14.4/drivers/net/ethernet/ti/icssg/
Dicssg_prueth_sr1.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
26 #include "../k3-cppi-desc-pool.h"
31 * implemented in firmware, but only 4 tx channels/threads in the Egress
34 * situation. So use Q0-Q2 as data queues and Q3 as management queue
41 * pool size to min size of 128 bytes since there are only 3 tx
62 config.addr_lo = cpu_to_le32(lower_32_bits(prueth->msmcram.pa)); in icssg_config_sr1()
63 config.addr_hi = cpu_to_le32(upper_32_bits(prueth->msmcram.pa)); in icssg_config_sr1()
64 config.rx_flow_id = cpu_to_le32(emac->rx_flow_id_base); /* flow id for host port */ in icssg_config_sr1()
65 config.rx_mgr_flow_id = cpu_to_le32(emac->rx_mgm_flow_id_base); /* for mgm ch */ in icssg_config_sr1()
[all …]
Dicssg_prueth.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
12 #include <linux/dma-mapping.h>
13 #include <linux/dma/ti-cppi5.h>
19 #include <linux/io-64-nonatomic-hi-lo.h>
37 #include "../k3-cppi-desc-pool.h"
56 struct prueth *prueth = emac->prueth; in emac_get_tx_ts()
65 memcpy_fromio(rsp, prueth->shram.va + addr, sizeof(*rsp)); in emac_get_tx_ts()
89 !emac->tx_ts_skb[tsr.cookie]) { in tx_ts_work()
90 netdev_err(emac->ndev, "Invalid TX TS cookie 0x%x\n", in tx_ts_work()
[all …]