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/linux-6.14.4/Documentation/devicetree/bindings/ata/
Dahci-platform.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/ata/ahci-platform.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: AHCI SATA Controller
10 SATA nodes are defined to describe on-chip Serial ATA controllers.
13 It is possible, but not required, to represent each port as a sub-node.
14 It allows to enable each port independently when dealing with multiple
18 - Hans de Goede <[email protected]>
19 - Jens Axboe <[email protected]>
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Dahci-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ahci-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common Properties for Serial ATA AHCI controllers
10 - Hans de Goede <[email protected]>
11 - Damien Le Moal <[email protected]>
14 This document defines device tree properties for a common AHCI SATA
18 document doesn't constitute a DT-node binding by itself but merely
19 defines a set of common properties for the AHCI-compatible devices.
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Drockchip,dwc-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/rockchip,dwc-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC AHCI SATA controller for Rockchip devices
10 - Serge Semin <[email protected]>
14 implementation of the AHCI SATA controller found in Rockchip
22 - rockchip,rk3568-dwc-ahci
23 - rockchip,rk3588-dwc-ahci
25 - compatible
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Dsnps,dwc-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/snps,dwc-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC AHCI SATA controller
10 - Serge Semin <[email protected]>
14 implementation of the AHCI SATA controller.
20 - snps,dwc-ahci
21 - snps,spear-ahci
23 - compatible
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Dsnps,dwc-ahci-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/snps,dwc-ahci-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC AHCI SATA controller properties
10 - Serge Semin <[email protected]>
14 AHCI controller properties.
19 - $ref: ahci-common.yaml#
30 Basic DWC AHCI SATA clock sources like application AXI/AHB BIU clock,
31 PM-alive clock, RxOOB detection clock, embedded PHYs reference (Rx/Tx)
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Dbrcm,sata-brcm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/brcm,sata-brcm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom SATA3 AHCI Controller
10 SATA nodes are defined to describe on-chip Serial ATA controllers.
14 - Florian Fainelli <[email protected]>
17 - $ref: ahci-common.yaml#
22 - items:
23 - enum:
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Dbaikal,bt1-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/baikal,bt1-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Baikal-T1 SoC AHCI SATA controller
10 - Serge Semin <[email protected]>
13 AHCI SATA controller embedded into the Baikal-T1 SoC is based on the
14 DWC AHCI SATA v4.10a IP-core.
17 - $ref: snps,dwc-ahci-common.yaml#
21 const: baikal,bt1-ahci
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Dceva,ahci-1v84.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ceva,ahci-1v84.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ceva AHCI SATA Controller
10 - Mubin Sayyed <[email protected]>
11 - Radhey Shyam Pandey <[email protected]>
14 The Ceva SATA controller mostly conforms to the AHCI interface with some
15 special extensions to add functionality, is a high-performance dual-port
16 SATA host controller with an AHCI compliant command layer which supports
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Dsata_highbank.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Calxeda AHCI SATA Controller
10 The Calxeda SATA controller mostly conforms to the AHCI interface
15 - Andre Przywara <[email protected]>
19 const: calxeda,hb-ahci
27 dma-coherent: true
29 calxeda,pre-clocks:
35 calxeda,post-clocks:
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/linux-6.14.4/drivers/ata/
Dahci_platform.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AHCI SATA platform driver
5 * Copyright 2004-2005 Red Hat, Inc.
21 #include "ahci.h"
23 #define DRV_NAME "ahci"
45 struct device *dev = &pdev->dev; in ahci_probe()
47 const struct ata_port_info *port; in ahci_probe() local
59 if (device_is_compatible(dev, "hisilicon,hisi-ahci")) in ahci_probe()
60 hpriv->flags |= AHCI_HFLAG_NO_FBS | AHCI_HFLAG_NO_NCQ; in ahci_probe()
62 port = device_get_match_data(dev); in ahci_probe()
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Dahci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ahci.c - AHCI SATA support
6 * Please ALWAYS copy linux-[email protected]
9 * Copyright 2004-2005 Red Hat, Inc.
12 * as Documentation/driver-api/libata.rst
14 * AHCI hardware documentation:
25 #include <linux/dma-mapping.h>
32 #include <linux/ahci-remap.h>
33 #include <linux/io-64-nonatomic-lo-hi.h>
34 #include "ahci.h"
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Dlibahci_platform.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AHCI SATA platform library
5 * Copyright 2004-2005 Red Hat, Inc.
26 #include "ahci.h"
37 * ahci_platform_enable_phys - Enable PHYs
40 * This function enables all the PHYs found in hpriv->phys, if any.
51 for (i = 0; i < hpriv->nports; i++) { in ahci_platform_enable_phys()
55 rc = phy_init(hpriv->phys[i]); in ahci_platform_enable_phys()
59 rc = phy_set_mode(hpriv->phys[i], PHY_MODE_SATA); in ahci_platform_enable_phys()
61 phy_exit(hpriv->phys[i]); in ahci_platform_enable_phys()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0
10 uses pata-platform driver to enable the relevant driver in the
21 If you want to use an ATA hard disk, ATA tape drive, ATA CD-ROM or
62 <file:Documentation/admin-guide/kernel-parameters.txt>.
76 This option adds support for ATA-related ACPI objects.
98 bool "SATA Port Multiplier support"
102 This option adds support for SATA Port Multipliers
107 comment "Controllers with non-SFF native interface"
110 tristate "AHCI SATA support"
114 This option enables support for AHCI Serial ATA.
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Dacard-ahci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * acard-ahci.c - ACard AHCI SATA support
7 * Please ALWAYS copy linux-[email protected]
13 * as Documentation/driver-api/libata.rst
15 * AHCI hardware documentation:
26 #include <linux/dma-mapping.h>
33 #include "ahci.h"
35 #define DRV_NAME "acard-ahci"
70 AHCI_SHT("acard-ahci"),
115 struct ahci_host_priv *hpriv = host->private_data; in acard_ahci_pci_device_suspend()
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Dahci_sunxi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Allwinner sunxi AHCI SATA platform driver
7 * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
20 #include "ahci.h"
22 #define DRV_NAME "ahci-sunxi"
28 "Enable support for sata port multipliers, only use if you use a pmp!");
118 if (--timeout == 0) { in ahci_sunxi_phy_init()
120 return -EIO; in ahci_sunxi_phy_init()
133 if (--timeout == 0) { in ahci_sunxi_phy_init()
135 return -EIO; in ahci_sunxi_phy_init()
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Dahci_brcm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Broadcom SATA3 AHCI Controller Driver
5 * Copyright © 2009-2015 Broadcom Corporation
22 #include "ahci.h"
24 #define DRV_NAME "brcm-ahci"
28 #define MMIO_ENDIAN_SHIFT 0 /* CPU->AHCI */
29 #define DMADESC_ENDIAN_SHIFT 2 /* AHCI->DDR */
30 #define DMADATA_ENDIAN_SHIFT 4 /* AHCI->DDR */
51 /* On big-endian MIPS, buses are reversed to big endian, so switch them back */
53 #define DATA_ENDIAN 2 /* AHCI->DDR inbound accesses */
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Dahci_mvebu.c2 * AHCI glue platform driver for Marvell EBU SOCs
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
20 #include "ahci.h"
22 #define DRV_NAME "ahci-mvebu"
42 writel(0, hpriv->mmio + AHCI_WINDOW_CTRL(i)); in ahci_mvebu_mbus_config()
43 writel(0, hpriv->mmio + AHCI_WINDOW_BASE(i)); in ahci_mvebu_mbus_config()
44 writel(0, hpriv->mmio + AHCI_WINDOW_SIZE(i)); in ahci_mvebu_mbus_config()
47 for (i = 0; i < dram->num_cs; i++) { in ahci_mvebu_mbus_config()
48 const struct mbus_dram_window *cs = dram->cs + i; in ahci_mvebu_mbus_config()
50 writel((cs->mbus_attr << 8) | in ahci_mvebu_mbus_config()
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Dahci_dwc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DWC AHCI SATA Platform driver
23 #include "ahci.h"
25 #define DRV_NAME "ahci-dwc"
29 /* DWC AHCI SATA controller specific registers */
95 /* Baikal-T1 AHCI SATA specific registers */
127 struct ahci_dwc_host_priv *dpriv = hpriv->plat_data; in ahci_bt1_init()
134 dev_err(&dpriv->pdev->dev, "No system clocks specified\n"); in ahci_bt1_init()
135 return -EINVAL; in ahci_bt1_init()
145 dev_err(&dpriv->pdev->dev, "Couldn't assert the resets\n"); in ahci_bt1_init()
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Dahci_seattle.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * AMD Seattle AHCI SATA driver
8 * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
20 #include "ahci.h"
28 * 28...8 RW OD6.2...OD0.0 (3bits per port, 1 bit per LED)
31 * 3:0 RO Number of ports (0 means no port supported)
41 #define DRV_NAME "ahci-seattle"
81 struct ahci_host_priv *hpriv = ap->host->private_data; in seattle_transmit_led_message()
82 struct ahci_port_priv *pp = ap->private_data; in seattle_transmit_led_message()
83 struct seattle_plat_data *plat_data = hpriv->plat_data; in seattle_transmit_led_message()
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Dahci_dm816.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DaVinci DM816 AHCI SATA platform driver
16 #include "ahci.h"
18 #define AHCI_DM816_DRV_NAME "ahci-dm816"
55 * We should have divided evenly - if not, return an invalid in ahci_dm816_get_mpy_bits()
58 return -1; in ahci_dm816_get_mpy_bits()
69 * keep-alive clock and the external reference clock. We need the in ahci_dm816_phy_init()
72 if (hpriv->n_clks < 2) { in ahci_dm816_phy_init()
74 return -EINVAL; in ahci_dm816_phy_init()
77 refclk_rate = clk_get_rate(hpriv->clks[1].clk); in ahci_dm816_phy_init()
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Dsata_highbank.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Calxeda Highbank AHCI SATA platform driver
6 * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
25 #include "ahci.h"
53 /* Each of the 6 phys can have up to 4 sata ports attached to i. Map 0-based
88 static inline int sgpio_bit_shift(struct ecx_plat_data *pdata, u32 port, in sgpio_bit_shift() argument
91 return 1 << (3 * pdata->port_to_sgpio[port] + shift); in sgpio_bit_shift()
94 static void ecx_parse_sgpio(struct ecx_plat_data *pdata, u32 port, u32 state) in ecx_parse_sgpio() argument
97 pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port, in ecx_parse_sgpio()
100 pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port, in ecx_parse_sgpio()
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Dahci_qoriq.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale QorIQ AHCI SATA platform driver
18 #include "ahci.h"
20 #define DRV_NAME "ahci-qoriq"
22 /* port register definition */
31 /* port register default value */
70 { .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
71 { .compatible = "fsl,ls1028a-ahci", .data = (void *)AHCI_LS1028A},
72 { .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
73 { .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
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Dahci_ceva.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * CEVA AHCI SATA platform driver
6 * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
16 #include "ahci.h"
64 /* Port Control Register Bit Definitions */
73 #define DRV_NAME "ahci-ceva"
78 MODULE_PARM_DESC(rx_watermark, "RxWaterMark value (0 - 0x80)");
82 /* Port Phy2Cfg Register */
124 void __iomem *mmio = hpriv->mmio; in ahci_ceva_setup()
125 struct ceva_ahci_priv *cevapriv = hpriv->plat_data; in ahci_ceva_setup()
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Dlibahci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * libahci.c - Common AHCI SATA low-level routines
6 * Please ALWAYS copy linux-[email protected]
9 * Copyright 2004-2005 Red Hat, Inc.
12 * as Documentation/driver-api/libata.rst
14 * AHCI hardware documentation:
27 #include <linux/dma-mapping.h>
33 #include "ahci.h"
203 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
236 * ahci_rpm_get_port - Make sure the port is powered on
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Dahci.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * ahci.h - Common AHCI SATA definitions and declarations
6 * Please ALWAYS copy linux-[email protected]
9 * Copyright 2004-2005 Red Hat, Inc.
12 * as Documentation/driver-api/libata.rst
14 * AHCI hardware documentation:
74 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
80 HOST_RESET = BIT(0), /* reset controller; self-clear */
83 HOST_AHCI_EN = BIT(31), /* AHCI enabled */
92 HOST_CAP_FBS = BIT(16), /* FIS-based switching support */
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