1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dma/nvidia,tegra210-adma.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra Audio DMA (ADMA) controller
8
9description: |
10  The Tegra Audio DMA controller is used for transferring data
11  between system memory and the Audio Processing Engine (APE).
12
13maintainers:
14  - Jon Hunter <[email protected]>
15
16properties:
17  compatible:
18    oneOf:
19      - enum:
20          - nvidia,tegra210-adma
21          - nvidia,tegra186-adma
22      - items:
23          - enum:
24              - nvidia,tegra234-adma
25              - nvidia,tegra194-adma
26          - const: nvidia,tegra186-adma
27
28  reg:
29    description:
30      The 'page' region describes the address space of the page
31      used for accessing the DMA channel registers. The 'global'
32      region describes the address space of the global DMA registers.
33      In the absence of the 'reg-names' property, there must be a
34      single entry that covers the address space of the global DMA
35      registers and the DMA channel registers.
36    minItems: 1
37    maxItems: 2
38
39  reg-names:
40    minItems: 1
41    maxItems: 2
42
43  interrupts:
44    description: |
45      Should contain all of the per-channel DMA interrupts in
46      ascending order with respect to the DMA channel index.
47    minItems: 1
48    maxItems: 32
49
50  clocks:
51    description: Must contain one entry for the ADMA module clock
52    maxItems: 1
53
54  clock-names:
55    const: d_audio
56
57  "#dma-cells":
58    description: |
59      The first cell denotes the receive/transmit request number and
60      should be between 1 and the maximum number of requests supported.
61      This value corresponds to the RX/TX_REQUEST_SELECT fields in the
62      ADMA_CHn_CTRL register.
63    const: 1
64
65  dma-channel-mask:
66    maxItems: 1
67
68required:
69  - compatible
70  - reg
71  - interrupts
72  - clocks
73  - clock-names
74
75allOf:
76  - $ref: dma-controller.yaml#
77  - if:
78      properties:
79        compatible:
80          contains:
81            enum:
82              - nvidia,tegra210-adma
83    then:
84      properties:
85        reg:
86          items:
87            - description: Full address space range of DMA registers.
88
89  - if:
90      properties:
91        compatible:
92          contains:
93            enum:
94              - nvidia,tegra186-adma
95    then:
96      anyOf:
97        - properties:
98            reg:
99              items:
100                - description: Full address space range of DMA registers.
101        - properties:
102            reg:
103              items:
104                - description: Channel Page address space range of DMA registers.
105            reg-names:
106              items:
107                - const: page
108        - properties:
109            reg:
110              items:
111                - description: Channel Page address space range of DMA registers.
112                - description: Global Page address space range of DMA registers.
113            reg-names:
114              items:
115                - const: page
116                - const: global
117
118additionalProperties: false
119
120examples:
121  - |
122    #include <dt-bindings/interrupt-controller/arm-gic.h>
123    #include<dt-bindings/clock/tegra210-car.h>
124
125    dma-controller@702e2000 {
126        compatible = "nvidia,tegra210-adma";
127        reg = <0x702e2000 0x2000>;
128        interrupt-parent = <&tegra_agic>;
129        interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
130                     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
131                     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
132                     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
133                     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
134                     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
135                     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
136                     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
137                     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
138                     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
139                     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
140                     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
141                     <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
142                     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
143                     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
144                     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
145                     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
146                     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
147                     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
148                     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
149                     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
150                     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
151        clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
152        clock-names = "d_audio";
153        #dma-cells = <1>;
154    };
155
156...
157