/linux-6.14.4/arch/arm64/boot/dts/qcom/ |
D | msm8992-lg-h815.dts | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 8 /dts-v1/; 13 #include <dt-bindings/leds/common.h> 16 /delete-node/ &cont_splash_mem; 19 /delete-node/ &dfps_data_mem; 24 chassis-type = "handset"; 26 qcom,msm-id = <0xfb 0x0>; 27 qcom,pmic-id = <0x10009 0x1000a 0x0 0x0>; 28 qcom,board-id = <0xb64 0x0>; 31 /delete-node/ psci; [all …]
|
/linux-6.14.4/Documentation/hwmon/ |
D | lm93.rst | 10 Addresses scanned: I2C 0x2c-0x2e 18 Addresses scanned: I2C 0x2c-0x2e 24 - Mark M. Hoffman <[email protected]> 25 - Ported to 2.6 by Eric J. Bowersox <[email protected]> 26 - Adapted to 2.6.20 by Carsten Emde <[email protected]> 27 - Modified for mainline integration by Hans J. Koch <[email protected]> 30 ----------------- 33 Set to non-zero to force some initializations (default is 0). 38 Configures in7 and in8 limit type, where 0 means absolute and non-zero 54 -------------------- [all …]
|
D | drivetemp.rst | 1 .. SPDX-License-Identifier: GPL-2.0 8 ---------- 10 ANS T13/1699-D 11 Information technology - AT Attachment 8 - ATA/ATAPI Command Set (ATA8-ACS) 14 Information technology - SCSI Primary Commands - 4 (SPC-4) 17 Information technology - SCSI / ATA Translation - 5 (SAT-5) 21 ----------- 34 ---------- 36 Reading the drive temperature may reset the spin down timer on some drives. 43 change its mode (meaning the drive will not spin up). It is unknown if other [all …]
|
/linux-6.14.4/drivers/gpu/drm/i915/gt/ |
D | selftest_rps.c | 1 // SPDX-License-Identifier: MIT 26 #define CPU_LATENCY 0 /* -1 to disable pm_qos, 0 to disable cstates */ 37 return -1; in cmp_u64() 49 return -1; in cmp_u32() 68 #define CS_GPR(x) GEN8_RING_CS_GPR(engine->mmio_base, x) in create_spin_counter() 76 obj = i915_gem_object_create_internal(vm->i915, 64 << 10); in create_spin_counter() 80 end = obj->base.size / sizeof(u32) - 1; in create_spin_counter() 113 loop = cs - base; in create_spin_counter() 134 GEM_BUG_ON(cs - base > end); in create_spin_counter() 190 mutex_lock(&rps->lock); in rps_set_check() [all …]
|
D | selftest_engine_pm.c | 1 // SPDX-License-Identifier: GPL-2.0 25 return *a - *b; in cmp_u64() 76 struct intel_engine_cs *engine = ce->engine; in __measure_timestamps() 77 u32 *sema = memset32(engine->status_page.addr + 1000, 0, 5); in __measure_timestamps() 78 u32 offset = i915_ggtt_offset(engine->status_page.vma); in __measure_timestamps() 96 cs = emit_srm(cs, RING_TIMESTAMP(engine->mmio_base), offset + 4000); in __measure_timestamps() 97 cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4004); in __measure_timestamps() 102 cs = emit_srm(cs, RING_TIMESTAMP(engine->mmio_base), offset + 4016); in __measure_timestamps() 103 cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4012); in __measure_timestamps() 117 while (READ_ONCE(sema[1]) == 0) /* wait for the gpu to catch up */ in __measure_timestamps() [all …]
|
D | selftest_execlists.c | 1 // SPDX-License-Identifier: MIT 24 #define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4) 47 tasklet_hi_schedule(&engine->sched_engine->tasklet); in wait_for_submit() 58 if (!READ_ONCE(engine->execlists.pending[0]) && is_active(rq)) in wait_for_submit() 62 return -ETIME; in wait_for_submit() 78 if (READ_ONCE(engine->execlists.pending[0])) in wait_for_reset() 84 if (READ_ONCE(rq->fence.error)) in wait_for_reset() 88 if (rq->fence.error != -EIO) { in wait_for_reset() 90 engine->name, in wait_for_reset() 91 rq->fence.context, in wait_for_reset() [all …]
|
/linux-6.14.4/drivers/of/unittest-data/ |
D | overlay.dtso | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 8 hvac_2: hvac-large-1 { 9 compatible = "ot,hvac-large"; 10 heat-range = <40 75>; 11 cool-range = <65 80>; 17 #address-cells = <1>; 18 #size-cells = <1>; 22 #address-cells = <1>; 23 #size-cells = <1>; [all …]
|
/linux-6.14.4/arch/sparc/include/asm/ |
D | backoff.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 10 * completion of the compare-and-swap instruction. Heavily 14 * When an atomic operation fails and needs to be retried, we spin a 16 * operation we double the spin count, realizing an exponential 19 * When we spin, we try to use an operation that will cause the 24 * On all cpus prior to SPARC-T4 we do three dummy reads of the 28 * For SPARC-T4 and later we have a special "pause" instruction 31 * unless a disrupting trap happens first. SPARC-T4 specifically 39 * on earlier chips, we shift the backoff value up by 7 bits. (Three
|
/linux-6.14.4/drivers/net/can/softing/ |
D | softing_main.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2008-2010 5 * - Kurt Van Dijck, EIA Electronics 15 #define TX_ECHO_SKB_MAX (((TXMAX+1)/2)-1) 19 * is online (ie. up 'n running, not sleeping, not busoff 27 return (can->state <= CAN_STATE_ERROR_PASSIVE); in canif_is_active() 33 if (card->pdat->generation >= 2) { in softing_set_reset_dpram() 34 spin_lock_bh(&card->spin); in softing_set_reset_dpram() 35 iowrite8(ioread8(&card->dpram[DPRAM_V2_RESET]) & ~1, in softing_set_reset_dpram() 36 &card->dpram[DPRAM_V2_RESET]); in softing_set_reset_dpram() [all …]
|
/linux-6.14.4/drivers/pinctrl/spacemit/ |
D | pinctrl-k1.c | 1 // SPDX-License-Identifier: GPL-2.0 13 #include <linux/pinctrl/pinconf-generic.h> 19 #include "../pinctrl-utils.h" 22 #include "pinctrl-k1.h" 25 * +---------+----------+-----------+--------+--------+----------+--------+ 27 * | up/down | strength | trigger | rate | detect | pull | mode | 28 * +---------+----------+-----------+--------+--------+----------+--------+ 128 return pctrl->regs + spacemit_pin_to_offset(pin); in spacemit_pin_to_reg() 144 const struct spacemit_pin *pdata = pctrl->data->data; in spacemit_get_pin() 147 for (i = 0; i < pctrl->data->npins; i++) { in spacemit_get_pin() [all …]
|
/linux-6.14.4/kernel/locking/ |
D | spinlock.c | 1 // SPDX-License-Identifier: GPL-2.0 10 * SMP and the DEBUG_SPINLOCK cases. (UP-nondebug inlines them) 33 * If lockdep is enabled then we use the non-preemption spin-ops 35 * not re-enabled during lock-acquire (which the preempt-spin-ops do): 63 * This could be a long-held lock. We both prepare to spin for a long 76 arch_##op##_relax(&lock->raw_lock); \ 92 arch_##op##_relax(&lock->raw_lock); \ 109 /* irq-disabling. We use the generic preemption-aware */ \ 118 * Build preemption-friendly versions of the following 119 * lock-spinning functions: [all …]
|
D | spinlock_rt.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * PREEMPT_RT substitution for spin/rw_locks 8 * - Contrary to plain rtmutexes, spinlocks and rwlocks are state 11 * during that time are redirected to the saved state so no wake up is 14 * - Non RT spin/rwlocks disable preemption and eventually interrupts. 29 * preserving. Take RCU nesting into account as spin/read/write_lock() can 40 lockdep_assert(!current->pi_blocked_on); in rtlock_lock() 49 rtlock_lock(&lock->lock); in __rt_spin_lock() 56 spin_acquire(&lock->dep_map, 0, 0, _RET_IP_); in rt_spin_lock() 64 spin_acquire(&lock->dep_map, subclass, 0, _RET_IP_); in rt_spin_lock_nested() [all …]
|
/linux-6.14.4/arch/x86/include/asm/ |
D | spinlock.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 16 * Simple spin lock operations. There are two variants, one clears IRQ's 19 * These are fair FIFO ticket locks, which support up to 2^16 CPUs. 24 /* How long a lock should spin before we consider blocking */ 30 * Read-write spinlocks, allowing multiple readers 35 * can "mix" irq-safe locks - any writer needs to get a 36 * irq-safe write-lock, but readers can get non-irqsafe 37 * read-locks. 39 * On x86, we implement read-write locks using the generic qrwlock with
|
/linux-6.14.4/Documentation/locking/ |
D | spinlocks.rst | 5 Lesson 1: Spin locks 20 there is only one thread-of-control within the region(s) protected by that 21 lock. This works well even under UP also, so the code does _not_ need to 22 worry about UP vs SMP issues: the spinlocks work correctly under both. 26 Documentation/memory-barriers.txt 33 spinlock for most things - using more than one spinlock can make things a 35 sequences that you **know** need to be split up: avoid it at all cost if you 45 NOTE! The spin-lock is safe only when you **also** use the lock itself 50 ---- 52 Lesson 2: reader-writer spinlocks. [all …]
|
D | rt-mutex-design.rst | 2 RT-mutex implementation design 12 Documentation/locking/rt-mutex.rst. Although this document does explain problems 22 ---------------------------- 49 A ---+ 52 C +----+ 54 B +--------> 59 ------------------------- 74 ----------- 80 - The PI chain is an ordered series of locks and processes that cause 86 - In this document, to differentiate from locks that implement [all …]
|
/linux-6.14.4/tools/testing/selftests/kvm/ |
D | set_memory_region_test.c | 1 // SPDX-License-Identifier: GPL-2.0 55 struct kvm_run *run = vcpu->run; in vcpu_worker() 60 * Loop until the guest is done. Re-enter the guest on all MMIO exits, in vcpu_worker() 67 if (run->exit_reason == KVM_EXIT_IO) { in vcpu_worker() 76 if (run->exit_reason != KVM_EXIT_MMIO) in vcpu_worker() 79 TEST_ASSERT(!run->mmio.is_write, "Unexpected exit mmio write"); in vcpu_worker() 80 TEST_ASSERT(run->mmio.len == 8, in vcpu_worker() 81 "Unexpected exit mmio size = %u", run->mmio.len); in vcpu_worker() 83 TEST_ASSERT(run->mmio.phys_addr == MEM_REGION_GPA, in vcpu_worker() 85 run->mmio.phys_addr); in vcpu_worker() [all …]
|
/linux-6.14.4/arch/arc/include/asm/ |
D | atomic-spinlock.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 7 * Non hardware assisted Atomic-R-M-W 8 * Locking would change to irq-disabling only (UP) and spinlocks (SMP) 25 WRITE_ONCE(v->counter, i); in arch_atomic_set() 37 v->counter c_op i; \ 48 * spin lock/unlock provides the needed smp_mb() before/after \ 51 temp = v->counter; \ 53 v->counter = temp; \ 66 * spin lock/unlock provides the needed smp_mb() before/after \ 69 orig = v->counter; \ [all …]
|
/linux-6.14.4/Documentation/devicetree/bindings/arm/ |
D | qcom.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Bjorn Andersson <[email protected]> 109 https://docs.kernel.org/arch/arm/google/chromebook-boot-flow.html 116 - items: 117 - enum: 118 - qcom,apq8016-sbc 119 - schneider,apq8016-hmibsc 120 - const: qcom,apq8016 [all …]
|
/linux-6.14.4/arch/arm64/kernel/ |
D | smp_spin_table.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Spin Table SMP initialisation 50 return -ENODEV; in smp_spin_table_cpu_init() 55 ret = of_property_read_u64(dn, "cpu-release-addr", in smp_spin_table_cpu_init() 58 pr_err("CPU %d: missing or invalid cpu-release-addr property\n", in smp_spin_table_cpu_init() 72 return -ENODEV; in smp_spin_table_cpu_prepare() 75 * The cpu-release-addr may or may not be inside the linear mapping. in smp_spin_table_cpu_prepare() 83 return -ENOMEM; in smp_spin_table_cpu_prepare() 87 * endianness of the kernel. Therefore, any boot-loaders that in smp_spin_table_cpu_prepare() 89 * boot-loader's endianness before jumping. This is mandated by in smp_spin_table_cpu_prepare() [all …]
|
/linux-6.14.4/drivers/gpu/drm/i915/gem/selftests/ |
D | i915_gem_context.c | 2 * SPDX-License-Identifier: MIT 42 int err = -ENODEV; in live_nop_switch() 52 if (!DRIVER_CAPS(i915)->has_logical_contexts) in live_nop_switch() 61 err = -ENOMEM; in live_nop_switch() 88 i915_request_await_dma_fence(this, &rq->fence); in live_nop_switch() 96 intel_gt_set_wedged(engine->gt); in live_nop_switch() 98 err = -EIO; in live_nop_switch() 106 nctx, engine->name, ktime_to_ns(times[1] - times[0])); in live_nop_switch() 108 err = igt_live_test_begin(&t, i915, __func__, engine->name); in live_nop_switch() 127 i915_request_await_dma_fence(this, &rq->fence); in live_nop_switch() [all …]
|
/linux-6.14.4/tools/memory-model/Documentation/ |
D | locking.txt | 4 Locking is well-known and the common use cases are straightforward: Any 9 However, developers who would like to also access lock-protected shared 14 -------------------------- 51 ------------------------------- 86 Double-Checked Locking 87 ---------------------- 90 double-checked locking work correctly, This litmus test illustrates 93 /* See Documentation/litmus-tests/locking/DCL-broken.litmus. */ 118 /* See Documentation/litmus-tests/locking/DCL-fixed.litmus. */ 143 In short, if you access a lock-protected variable without holding the [all …]
|
/linux-6.14.4/tools/testing/selftests/rcutorture/bin/ |
D | jitterstart.sh | 2 # SPDX-License-Identifier: GPL-2.0+ 4 # Start up the specified number of jitter.sh scripts in the background. 6 # Usage: . jitterstart.sh n jittering-dir duration [ sleepmax [ spinmax ] ] 8 # n: Number of jitter.sh scripts to start up. 9 # jittering-dir: Directory in which to put "jittering" file. 12 # spinmax: Maximum microseconds to spin, defaults to one millisecond. 19 if test -z "$jitter_n" 25 if test -z "$jittering_dir"
|
/linux-6.14.4/Documentation/admin-guide/laptops/ |
D | laptop-mode.rst | 2 How to conserve battery power using laptop-mode 12 ------------ 14 Laptop mode is used to minimize the time that the hard disk needs to be spun up, 31 ------------ 41 located in /etc/default/laptop-mode on Debian-based systems, or in 42 /etc/sysconfig/laptop-mode on other systems. 52 ------- 54 * The downside of laptop mode is that you have a chance of losing up to 10 64 * If you mount some of your ext3/reiserfs filesystems with the -n option, then 67 wrong options -- or it will fail because it cannot write to /etc/mtab. [all …]
|
/linux-6.14.4/Documentation/core-api/ |
D | swiotlb.rst | 1 .. SPDX-License-Identifier: GPL-2.0 19 These APIs use the device DMA attributes and kernel-wide settings to determine 30 --------------- 33 only provide 32-bit DMA addresses. By allocating bounce buffer memory below 40 directed to guest memory that is unencrypted. CoCo VMs set a kernel-wide option 42 up as unencrypted. The host does DMA I/O to/from the bounce buffer memory, and 50 mappings are set up for a DMA operation to/from a device that is considered 54 IOMMU access control is per-granule, the untrusted device can gain access to 60 ------------------ 85 ------------------------------ [all …]
|
/linux-6.14.4/Documentation/trace/ |
D | hwlat_detector.rst | 6 ------------- 17 even know that they are occurring. SMIs are instead set up by BIOS code 36 ------ 50 - width - time period to sample with CPUs held (usecs) 52 - window - total period of sampling, width being inside (usecs) 55 for every 1,000,000 usecs (1s) the hwlat detector will spin for 500,000 usecs 74 - tracing_threshold - minimum latency value to be considered (usecs) 75 - tracing_max_latency - maximum hardware latency actually observed (usecs) 76 - tracing_cpumask - the CPUs to move the hwlat thread across 77 - hwlat_detector/width - specified amount of time to spin within window (usecs) [all …]
|