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/aosp_15_r20/external/pytorch/c10/core/
H A DBackend.h39 SparseCsrCPU, enumerator
103 } else if (t == DispatchKey::SparseCsrCPU) { in dispatchKeyToBackend()
104 return Backend::SparseCsrCPU; in dispatchKeyToBackend()
181 case Backend::SparseCsrCPU: in backendToDispatchKey()
182 return DispatchKey::SparseCsrCPU; in backendToDispatchKey()
225 case Backend::SparseCsrCPU: in backendToDeviceType()
320 case Backend::SparseCsrCPU: in toString()
321 return "SparseCsrCPU"; in toString()
376 case Backend::SparseCsrCPU: in isSparseCsr()
H A DDispatchKey.cpp350 {"SparseCsrCPU", c10::DispatchKey::SparseCsrCPU}, in parseDispatchKey()
H A DLayout.h42 case Backend::SparseCsrCPU: in layout_from_backend()
H A DDispatchKeySet.h82 // - "SparseCsr": SparseCsrCPU, SparseCsrCUDA, ...
/aosp_15_r20/external/pytorch/aten/src/ATen/native/
H A Dnative_functions.yaml341 SparseCsrCPU, SparseCsrCUDA: abs_sparse_csr
351 SparseCsrCPU, SparseCsrCUDA: abs_sparse_csr_
360 SparseCsrCPU, SparseCsrCUDA: abs_sparse_csr_out
403 SparseCsrCPU, SparseCsrCUDA: angle_sparse_csr
410 SparseCsrCPU, SparseCsrCUDA: angle_sparse_csr_out
428 SparseCsrCPU, SparseCsrCUDA: sgn_sparse_csr
437 SparseCsrCPU, SparseCsrCUDA: sgn_sparse_csr_
448 SparseCsrCPU, SparseCsrCUDA: sgn_sparse_csr_out
475 SparseCsrCPU, SparseCsrCUDA: conj_physical_sparse_csr
487 SparseCsrCPU, SparseCsrCUDA: conj_physical_sparse_csr_out
[all …]
/aosp_15_r20/external/pytorch/tools/test/
H A Dtest_executorch_gen.py39 SparseCsrCPU: add_out_sparse_csr_cpu
50 SparseCsrCPU, SparseCsrCUDA: add_sparse_csr
65 SparseCsrCPU, SparseCsrCUDA: mul_out_sparse_csr
74 SparseCsrCPU, SparseCsrCUDA: mul_sparse_csr
/aosp_15_r20/external/pytorch/aten/src/ATen/
H A DSparseCsrTensorImpl.cpp57 TORCH_INTERNAL_ASSERT(((key_set.has(DispatchKey::SparseCsrCPU) && device().type() == kCPU) in SparseCsrTensorImpl()
60 … || (key_set.has(DispatchKey::SparseCsrCPU) && device().type() == kMeta) // fake tensor in SparseCsrTensorImpl()
/aosp_15_r20/external/pytorch/torch/
H A D_python_dispatcher.py22 E.g. FPGA, SparseCsrCPU
/aosp_15_r20/external/pytorch/aten/src/ATen/native/sparse/
H A DSparseCsrTensor.cpp345 // SparseCsrCPU, SparseCsrCUDA, and SparseCsrTensorImpl exists because
358 dispatch_key = DispatchKey::SparseCsrCPU; in new_compressed_tensor()
/aosp_15_r20/external/pytorch/torch/testing/_internal/opinfo/definitions/
H A Dsparse.py380 …ementedError: Could not run 'aten::sum.IntList_out' with arguments from the 'SparseCsrCPU' backend.
/aosp_15_r20/external/pytorch/torchgen/
H A Dmodel.py180 SparseCsrCPU = auto() variable in DispatchKey
277 DispatchKey.SparseCsrCPU,