Searched full:rs0 (Results 1 – 12 of 12) sorted by relevance
| /linux-6.14.4/arch/arm64/kernel/ |
| D | sleep.S | 14 * @rs0: register containing affinity level 0 bit shift
25 *compute_mpidr_hash(u32 rs0, u32 rs1, u32 rs2, u32 rs3, u64 mpidr, u64 mask) {
32 * dst = (aff0 >> rs0 | aff1 >> rs1 | aff2 >> rs2 | aff3 >> rs3);
34 * Input registers: rs0, rs1, rs2, rs3, mpidr, mask
39 .macro compute_mpidr_hash dst, rs0, rs1, rs2, rs3, mpidr, mask
42 lsr \dst ,\dst, \rs0 // dst=aff0>>rs0
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| /linux-6.14.4/arch/arm/kernel/ |
| D | sleep.S | 15 * @rs0: register containing affinity level 0 bit shift
25 *compute_mpidr_hash(u32 rs0, u32 rs1, u32 rs2, u32 mpidr, u32 mask) {
31 * dst = (aff0 >> rs0 | aff1 >> rs1 | aff2 >> rs2);
33 * Input registers: rs0, rs1, rs2, mpidr, mask
38 .macro compute_mpidr_hash dst, rs0, rs1, rs2, mpidr, mask
41 ARM( mov \dst, \dst, lsr \rs0 ) @ dst=aff0>>rs0
42 THUMB( lsr \dst, \dst, \rs0 )
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| /linux-6.14.4/include/linux/rtc/ |
| D | ds1685.h | 154 #define RTC_CTRL_A_RS_MASK 0x0f /* RS3 + RS2 + RS1 + RS0 */
291 * Periodic rates are selected by setting the RS3-RS0 bits in Control
295 * E32K overrides the settings of RS3-RS0 and outputs a frequency of 32768Hz
311 /* E32K RS3 RS2 RS1 RS0 */
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| /linux-6.14.4/Documentation/devicetree/bindings/net/ |
| D | sff,sfp.yaml | 60 GPIO phandle and a specifier of the Rx Signaling Rate Select (AKA RS0)
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| /linux-6.14.4/drivers/edac/ |
| D | pnd2_edac.h | 223 u32 rs0 : 5; member
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| D | pnd2_edac.c | 979 daddr->rank = dnv_get_bit(pmiaddr, dmap[pmiidx].rs0 + 13, 0); in dnv_pmi2mem()
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| /linux-6.14.4/arch/sh/kernel/cpu/sh4a/ |
| D | clock-sh7724.c | 285 CLKDEV_CON_ID("rs0", &mstp_clks[HWBLK_RSMEM]),
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| /linux-6.14.4/drivers/net/phy/ |
| D | sfp.c | 1721 seq_printf(s, "rs0: %d\n", !!(sfp->state & SFP_F_RS0)); in sfp_debug_state_show()
2044 * SFF-8079 reveals that it is understood that RS0 will be low for in sfp_module_parse_rate_select()
2080 * Channel 1.0625/2.125/4.25 Gbd modes. Note that RS0 in sfp_module_parse_rate_select()
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| /linux-6.14.4/drivers/gpu/drm/i915/gt/ |
| D | intel_gt_regs.h | 1368 #define REDSAVES (1 << 3) /* no context save if was idle during rs0 */
1369 #define REDRESTORES (1 << 2) /* no restore if was idle during rs0 */
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| /linux-6.14.4/drivers/net/ethernet/intel/ixgbe/ |
| D | ixgbe_common.c | 4376 /* Set RS0 */ in ixgbe_set_soft_rate_select_speed()
4381 hw_dbg(hw, "Failed to read Rx Rate Select RS0\n"); in ixgbe_set_soft_rate_select_speed()
4391 hw_dbg(hw, "Failed to write Rx Rate Select RS0\n"); in ixgbe_set_soft_rate_select_speed()
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| D | ixgbe_82599.c | 630 * Set module link speed via RS0/RS1 rate select pins.
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| /linux-6.14.4/drivers/rtc/ |
| D | rtc-ds1685.c | 1146 /* Clear RS3-RS0 in Control A. */ in ds1685_rtc_probe()
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