| /linux-6.14.4/Documentation/devicetree/bindings/soc/fsl/cpm_qe/ |
| D | fsl,qe.yaml | 4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe.yaml#
7 title: Freescale QUICC Engine module (QE)
13 This represents qe module that is installed on PowerQUICC II Pro.
20 the "root" qe node, using the common properties from there.
21 The description below applies to the qe of MPC8360 and
27 - const: fsl,qe
38 enum: [QE, CPM, CPM2]
44 fsl,qe-num-riscs:
46 description: define how many RISC engines the QE has.
48 fsl,qe-snums:
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| D | fsl,qe-firmware.yaml | 4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-firmware.yaml#
19 inside a QE node that needs it. Doing so eliminates the need for a
20 fsl,firmware-phandle property. Other QE nodes that need the same firmware
22 in the first QE node.
30 - fsl,qe-firmware
45 qe-firmware {
46 compatible = "fsl,qe-firmware";
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| D | fsl,qe-si.yaml | 4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-si.yaml#
13 The SI manages the routing of eight TDM lines to the QE block serial drivers,
21 - fsl,ls1043-qe-si
22 - const: fsl,t1040-qe-si
24 - fsl,t1040-qe-si
38 compatible = "fsl,t1040-qe-si";
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| D | fsl,qe-ic.yaml | 4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-ic.yaml#
14 const: fsl,qe-ic
21 - description: QE interrupt
22 - description: QE critical
23 - description: QE error
42 compatible = "fsl,qe-ic";
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| D | fsl,qe-siram.yaml | 4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-siram.yaml#
20 - fsl,ls1043-qe-siram
21 - const: fsl,t1040-qe-siram
22 - const: fsl,t1040-qe-siram
36 compatible = "fsl,t1040-qe-siram";
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| D | fsl,qe-ucc-qmc.yaml | 4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-ucc-qmc.yaml#
7 title: PowerQUICC QE QUICC Multichannel Controller (QMC)
21 - const: fsl,qe-ucc-qmc
35 description: UCC interrupt line in the QE interrupt controller
44 TSA serial interface (dt-bindings/soc/qe-fsl,tsa.h defines these
79 - const: fsl,qe-ucc-qmc-hdlc
152 #include <dt-bindings/soc/qe-fsl,tsa.h>
155 compatible = "fsl,mpc8321-ucc-qmc", "fsl,qe-ucc-qmc";
189 "fsl,qe-ucc-qmc-hdlc",
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| D | fsl,qe-muram.yaml | 4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-muram.yaml#
17 - const: fsl,qe-muram
40 - const: fsl,qe-muram-data
61 compatible = "fsl,qe-muram", "fsl,cpm-muram";
67 compatible = "fsl,qe-muram-data",
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| /linux-6.14.4/drivers/soc/fsl/qe/ |
| D | qe.c | 11 * QUICC Engine (QE).
30 #include <soc/fsl/qe/immap_qe.h>
31 #include <soc/fsl/qe/qe.h>
54 struct device_node *qe; in qe_get_device_node() local
57 * Newer device trees have an "fsl,qe" compatible property for the QE in qe_get_device_node()
60 qe = of_find_compatible_node(NULL, NULL, "fsl,qe"); in qe_get_device_node()
61 if (qe) in qe_get_device_node()
62 return qe; in qe_get_device_node()
63 return of_find_node_by_type(NULL, "qe"); in qe_get_device_node()
68 struct device_node *qe; in get_qe_base() local
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| D | Kconfig | 3 # QE Communication options
7 bool "QUICC Engine (QE) framework support"
13 The QUICC Engine (QE) is a new generation of communications
16 for a machine with a QE coprocessor.
37 tristate "CPM/QE TSA support"
42 Freescale CPM/QE Time Slot Assigner (TSA)
49 tristate "CPM/QE QMC support"
54 Freescale CPM/QE QUICC Multichannel Controller
69 QE USB Controller support
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| D | qe_tdm.c | 8 * QE TDM API Set - TDM specific routines implementations.
13 #include <soc/fsl/qe/qe_tdm.h>
47 pr_err("QE-TDM: Invalid rx-sync-clock property\n"); in ucc_of_parse_tdm()
51 pr_err("QE-TDM: Invalid rx-sync-clock property\n"); in ucc_of_parse_tdm()
60 pr_err("QE-TDM: Invalid tx-sync-clock property\n"); in ucc_of_parse_tdm()
64 pr_err("QE-TDM: Invalid tx-sync-clock property\n"); in ucc_of_parse_tdm()
70 pr_err("QE-TDM: Invalid tx-timeslot-mask property\n"); in ucc_of_parse_tdm()
78 pr_err("QE-TDM: Invalid rx-timeslot-mask property\n"); in ucc_of_parse_tdm()
86 pr_err("QE-TDM: No fsl,tdm-id property for this UCC\n"); in ucc_of_parse_tdm()
100 pr_err("QE-TDM: No tdm-framer-type property for UCC\n"); in ucc_of_parse_tdm()
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| /linux-6.14.4/drivers/net/ethernet/chelsio/cxgb4/ |
| D | sched.c | 82 struct sched_queue_entry *qe; in t4_sched_bind_unbind_op() local
84 qe = (struct sched_queue_entry *)arg; in t4_sched_bind_unbind_op()
92 fw_class = bind ? qe->param.class : FW_SCHED_CLS_NONE; in t4_sched_bind_unbind_op()
93 fw_param = (fw_mnem | FW_PARAMS_PARAM_YZ_V(qe->cntxt_id)); in t4_sched_bind_unbind_op()
137 struct sched_queue_entry *qe; in t4_sched_entry_lookup() local
139 list_for_each_entry(qe, &e->entry_list, list) { in t4_sched_entry_lookup()
140 if (qe->cntxt_id == val) { in t4_sched_entry_lookup()
141 found = qe; in t4_sched_entry_lookup()
173 struct sched_queue_entry *qe = NULL; in cxgb4_sched_queue_lookup() local
181 qe = t4_sched_entry_lookup(pi, SCHED_QUEUE, txq->q.cntxt_id); in cxgb4_sched_queue_lookup()
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| /linux-6.14.4/drivers/net/ethernet/sun/ |
| D | sunqe.c | 118 printk(KERN_ERR "QuadEther: Cannot reset QE channel!\n"); in qe_stop()
409 /* Per-QE receive interrupt service routine. Just like on the happy meal
431 int len = (flags & RXD_LENGTH) - 4; /* QE adds ether FCS size to len */ in qe_rx()
464 /* Interrupts for all QE's get filtered out via the QEC master controller,
465 * so we just run through each qe and check to see who is signaling
655 /* Program the qe with the new filter value. */ in qe_set_multicast()
734 /* Set the local memsize register, divided up to one piece per QE channel. */ in qec_init_once()
738 /* Divide up the local QEC memory amongst the 4 QE receiver and in qec_init_once()
837 struct sunqe *qe; in qec_ether_init() local
849 qe = netdev_priv(dev); in qec_ether_init()
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| /linux-6.14.4/include/soc/fsl/qe/ |
| D | immap_qe.h | 3 * QUICC Engine (QE) Internal Memory Map.
4 * The Internal Memory Map for devices with QE on them. This
5 * is the superset of all QE devices (8360, etc.).
22 /* QE I-RAM */
31 /* QE Interrupt Controller */
56 __be32 cecr; /* QE command register */
57 __be32 ceccr; /* QE controller configuration register */
58 __be32 cecdr; /* QE command data register */
60 __be16 ceter; /* QE timer event register */
62 __be16 cetmr; /* QE timers mask register */
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| D | qe.h | 9 * QUICC Engine (QE) external definitions and structure.
21 #include <soc/fsl/qe/immap_qe.h>
28 #define QE_NUM_OF_SNUM 256 /* There are 256 serial number in QE */
87 /* Export QE common operations */
157 /* QE PIO */
220 /* QE internal API */
279 /* Structure that defines QE firmware binary files.
326 /* Upload a firmware to the QE */
338 /* QE USB */
368 /* QE extended filtering Table Lookup Key Size */
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| D | qe_tdm.h | 3 * Internal header file for QE TDM mode routines.
16 #include <soc/fsl/qe/immap_qe.h>
17 #include <soc/fsl/qe/qe.h>
19 #include <soc/fsl/qe/ucc.h>
20 #include <soc/fsl/qe/ucc_fast.h>
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| /linux-6.14.4/arch/powerpc/boot/dts/fsl/ |
| D | t1024si-post.dtsi | 43 qe:qe@ffe140000 { label
46 device_type = "qe";
47 compatible = "fsl,qe";
50 fsl,qe-num-riscs = <1>;
51 fsl,qe-num-snums = <28>;
65 &qe {
68 compatible = "fsl,qe-ic";
92 compatible = "fsl,qe-muram", "fsl,cpm-muram";
96 compatible = "fsl,qe-muram-data", "fsl,cpm-muram-data";
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| D | mpc8569si-post.dtsi | 191 &qe {
194 device_type = "qe";
195 compatible = "fsl,qe";
199 fsl,qe-num-riscs = <4>;
200 fsl,qe-num-snums = <46>;
204 compatible = "fsl,qe-ic";
213 compatible = "fsl,mpc8569-qe-gtm",
214 "fsl,qe-gtm", "fsl,gtm";
225 compatible = "fsl,mpc8569-qe-spi", "fsl,spi";
243 compatible = "fsl,mpc8569-qe-usb",
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| /linux-6.14.4/drivers/net/ethernet/brocade/bna/ |
| D | bna_tx_rx.c | 352 list_for_each_entry(mac, &rxf->mcast_active_q, qe) in bna_rxf_mcmac_get()
356 list_for_each_entry(mac, &rxf->mcast_pending_del_q, qe) in bna_rxf_mcmac_get()
368 list_for_each_entry(mchandle, &rxf->mcast_handle_q, qe) in bna_rxf_mchandle_get()
387 list_add_tail(&mchandle->qe, &rxf->mcast_handle_q); in bna_rxf_mchandle_attach()
410 list_del(&mchandle->qe); in bna_rxf_mcast_del()
427 struct bna_mac, qe); in bna_rxf_mcast_cfg_apply()
429 list_move_tail(&mac->qe, bna_mcam_mod_del_q(rxf->rx->bna)); in bna_rxf_mcast_cfg_apply()
437 struct bna_mac, qe); in bna_rxf_mcast_cfg_apply()
438 list_move_tail(&mac->qe, &rxf->mcast_active_q); in bna_rxf_mcast_cfg_apply()
475 struct bna_mac, qe); in bna_rxf_mcast_cfg_reset()
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| /linux-6.14.4/security/integrity/ima/ |
| D | ima_queue.c | 58 struct ima_queue_entry *qe, *ret = NULL; in ima_lookup_digest_entry() local
64 hlist_for_each_entry_rcu(qe, &ima_htable.queue[key], hnext) { in ima_lookup_digest_entry()
65 rc = memcmp(qe->entry->digests[ima_hash_algo_idx].digest, in ima_lookup_digest_entry()
67 if ((rc == 0) && (qe->entry->pcr == pcr)) { in ima_lookup_digest_entry()
68 ret = qe; in ima_lookup_digest_entry()
103 struct ima_queue_entry *qe; in ima_add_digest_entry() local
106 qe = kmalloc(sizeof(*qe), GFP_KERNEL); in ima_add_digest_entry()
107 if (qe == NULL) { in ima_add_digest_entry()
111 qe->entry = entry; in ima_add_digest_entry()
113 INIT_LIST_HEAD(&qe->later); in ima_add_digest_entry()
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| /linux-6.14.4/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/ |
| D | par_io.txt | 3 This node configures Parallel I/O ports for CPUs with QE support.
31 - compatible : should be "fsl,<chip>-qe-pario-bank",
32 "fsl,mpc8323-qe-pario-bank".
39 compatible = "fsl,mpc8360-qe-pario-bank",
40 "fsl,mpc8323-qe-pario-bank";
47 compatible = "fsl,mpc8360-qe-pario-bank",
48 "fsl,mpc8323-qe-pario-bank";
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| /linux-6.14.4/arch/powerpc/boot/dts/ |
| D | mpc836x_rdk.dts | 180 compatible = "fsl,mpc8360-qe-pario-bank",
181 "fsl,mpc8323-qe-pario-bank";
188 compatible = "fsl,mpc8360-qe-pario-bank",
189 "fsl,mpc8323-qe-pario-bank";
194 qe@100000 {
197 device_type = "qe";
198 compatible = "fsl,qe", "simple-bus";
205 fsl,qe-num-riscs = <2>;
206 fsl,qe-num-snums = <28>;
211 compatible = "fsl,qe-muram", "fsl,cpm-muram";
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| /linux-6.14.4/Documentation/devicetree/bindings/timer/ |
| D | fsl,gtm.txt | 6 "fsl,<chip>-qe-gtm", "fsl,qe-gtm", "fsl,gtm" for QE GTMs
24 compatible = "fsl,mpc8360-qe-gtm", "fsl,qe-gtm", "fsl,gtm";
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| /linux-6.14.4/arch/powerpc/platforms/85xx/ |
| D | twr_p102x.c | 22 #include <soc/fsl/qe/qe.h>
70 /* P1025 has pins muxed for QE and other functions. To in twr_p1025_setup_arch()
71 * enable QE UEC mode, we need to set bit QE0 for UCC1 in twr_p1025_setup_arch()
73 * and QE12 for QE MII management signals in PMUXCR in twr_p1025_setup_arch()
75 * Set QE mux bits in PMUXCR */ in twr_p1025_setup_arch()
92 * muxing from LBC to QE */ in twr_p1025_setup_arch()
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| /linux-6.14.4/drivers/scsi/bfa/ |
| D | bfa_fcpim.c | 25 list_add_tail(&(__itnim)->qe, &(__itnim)->fcpim->itnim_q)
29 list_del(&(__itnim)->qe); \
71 list_del(&(__ioim)->qe); \
72 list_add_tail(&(__ioim)->qe, &(__ioim)->fcpim->ioim_comp_q); \
287 struct list_head *qe, *qen; in bfa_fcpim_iocdisable() local
292 list_for_each_safe(qe, qen, &fcpim->itnim_q) { in bfa_fcpim_iocdisable()
293 itnim = (struct bfa_itnim_s *) qe; in bfa_fcpim_iocdisable()
374 struct list_head *qe, *qen; in bfa_fcpim_port_iostats() local
379 list_for_each_safe(qe, qen, &fcpim->itnim_q) { in bfa_fcpim_port_iostats()
380 itnim = (struct bfa_itnim_s *) qe; in bfa_fcpim_port_iostats()
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| /linux-6.14.4/drivers/mtd/spi-nor/ |
| D | sfdp.h | 57 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
60 * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
64 * clearing status register 2, including the QE bit. The 100b code is
67 * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
70 * - 011b: QE is bit 7 of status register 2. It is set via Write status
74 * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
79 * - 101b: QE is bit 1 of status register 2. Status register 1 is read using
81 * instruction 35h. QE is set via Write Status instruction 01h with
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