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/linux-6.14.4/Documentation/devicetree/bindings/phy/
Dqcom,msm8998-qmp-pcie-phy.yaml92 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
Dqcom,msm8996-qmp-pcie-phy.yaml140 resets = <&gcc GCC_PCIE_PHY_BCR>,
/linux-6.14.4/include/dt-bindings/clock/
Dqcom,gcc-sdx55.h100 #define GCC_PCIE_PHY_BCR 4 macro
Dqcom,gcc-sdx65.h104 #define GCC_PCIE_PHY_BCR 11 macro
Dqcom,sdx75-gcc.h181 #define GCC_PCIE_PHY_BCR 14 macro
Dqcom,sm7150-gcc.h163 #define GCC_PCIE_PHY_BCR 1 macro
Dqcom,sar2130p-gcc.h150 #define GCC_PCIE_PHY_BCR 13 macro
Dqcom,sm4450-gcc.h172 #define GCC_PCIE_PHY_BCR 8 macro
Dqcom,qcs615-gcc.h188 #define GCC_PCIE_PHY_BCR 9 macro
Dqcom,sm8750-gcc.h200 #define GCC_PCIE_PHY_BCR 9 macro
Dqcom,sm8550-gcc.h197 #define GCC_PCIE_PHY_BCR 13 macro
Dqcom,gcc-sdm845.h208 #define GCC_PCIE_PHY_BCR 3 macro
Dqcom,gcc-sm8450.h216 #define GCC_PCIE_PHY_BCR 14 macro
Dqcom,sm8650-gcc.h220 #define GCC_PCIE_PHY_BCR 13 macro
Dqcom,gcc-sm8150.h221 #define GCC_PCIE_PHY_BCR 8 macro
Dqcom,gcc-sm8250.h231 #define GCC_PCIE_PHY_BCR 19 macro
Dqcom,gcc-sc8180x.h265 #define GCC_PCIE_PHY_BCR 12 macro
Dqcom,gcc-msm8998.h284 #define GCC_PCIE_PHY_BCR 78 macro
Dqcom,gcc-msm8996.h325 #define GCC_PCIE_PHY_BCR 85 macro
Dqcom,x1e80100-gcc.h441 #define GCC_PCIE_PHY_BCR 44 macro
/linux-6.14.4/arch/arm/boot/dts/qcom/
Dqcom-sdx65.dtsi372 resets = <&gcc GCC_PCIE_PHY_BCR>;
Dqcom-sdx55.dtsi468 resets = <&gcc GCC_PCIE_PHY_BCR>;
/linux-6.14.4/drivers/clk/qcom/
Dgcc-sdx65.c1527 [GCC_PCIE_PHY_BCR] = { 0x44000 },
Dgcc-sdx55.c1567 [GCC_PCIE_PHY_BCR] = { 0x39000 },
Dgcc-sar2130p.c2243 [GCC_PCIE_PHY_BCR] = { 0x7f000 },

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