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/linux-6.14.4/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,ethdr.yaml4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml#
7 title: MediaTek Ethdr Device
14 ETHDR (ET High Dynamic Range) is a MediaTek internal HDR engine and is
20 one video backend and a mixer. ETHDR has two DMA function blocks, DS and ADL.
27 - const: mediatek,mt8195-disp-ethdr
29 - const: mediatek,mt8188-disp-ethdr
30 - const: mediatek,mt8195-disp-ethdr
66 - description: ethdr top clock
122 description: ETHDR input, usually from one of the MERGE blocks.
127 ETHDR output to the input of the next desired component in the
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Dmediatek,merge.yaml91 ETHDR or even from a different MERGE block
96 MERGE output to a DSC, DPI, DP_INTF, DSI, ETHDR, Write DMA, or
Dmediatek,padding.yaml16 width of a layer to be 2-pixel-align, or 4-pixel-align when ETHDR is enabled,
/linux-6.14.4/drivers/gpu/drm/mediatek/
Dmtk_disp_ovl_adaptor.c75 [OVL_ADAPTOR_TYPE_ETHDR] = "ethdr",
81 static const struct mtk_ddp_comp_funcs ethdr = { variable
109 [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, DDP_COMPONENT_ETHDR_MIXER, 0, &ethdr },
142 struct device *ethdr; in mtk_ovl_adaptor_layer_config() local
158 ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]; in mtk_ovl_adaptor_layer_config()
164 mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt); in mtk_ovl_adaptor_layer_config()
168 /* ETHDR is in 1T2P domain, width needs to be 2 pixels align */ in mtk_ovl_adaptor_layer_config()
206 mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt); in mtk_ovl_adaptor_layer_config()
489 { .compatible = "mediatek,mt8195-disp-ethdr", .data = (void *)OVL_ADAPTOR_TYPE_ETHDR },
526 * In the context of mediatek-drm, ETHDR, MDP_RDMA and Padding are in mtk_ovl_adaptor_is_comp_present()
Dmtk_ethdr.c366 "cannot get ethdr reset control\n"); in mtk_ethdr_probe()
383 { .compatible = "mediatek,mt8195-disp-ethdr"},
393 .name = "mediatek-disp-ethdr",
Dmtk_drm_drv.c326 .min_width = 2, /* 2-pixel align when ethdr is bypassed */
/linux-6.14.4/drivers/soc/mediatek/
Dmtk-mmsys.h104 * fixed value when the frame rate is decided, but ETHDR and
106 * MIXER has to sync with ETHDR by adjusting VSYNC length.
112 * ETHDR is bypassed, otherwise MIXER could wait too long and causing
/linux-6.14.4/arch/arm64/boot/dts/mediatek/
Dmt8188.dtsi2881 ethdr0: ethdr@1c114000 {
2882 compatible = "mediatek,mt8188-disp-ethdr", "mediatek,mt8195-disp-ethdr";
Dmt8195.dtsi3528 compatible = "mediatek,mt8195-disp-ethdr";