Searched +full:eic +full:- +full:sync (Results 1 – 6 of 6) sorted by relevance
| /linux-6.14.4/Documentation/devicetree/bindings/gpio/ |
| D | sprd,gpio-eic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/gpio/sprd,gpio-eic.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Unisoc EIC controller
11 - Orson Zhai <[email protected]>
12 - Baolin Wang <[email protected]>
13 - Chunyan Zhang <[email protected]>
16 The EIC is the abbreviation of external interrupt controller, which can
17 be used only in input mode. The Spreadtrum platform has 2 EIC controllers,
[all …]
|
| /linux-6.14.4/drivers/gpio/ |
| D | gpio-eic-sprd.c | 1 // SPDX-License-Identifier: GPL-2.0
17 /* EIC registers definition */
54 * The digital-chip EIC controller can support maximum 3 banks, and each bank
60 #define SPRD_EIC_BIT(x) ((x) & (SPRD_EIC_PER_BANK_NR - 1))
64 * The Spreadtrum EIC (external interrupt controller) can be used only in
67 * The Spreadtrum digital-chip EIC controller contains 4 sub-modules:
68 * debounce EIC, latch EIC, async EIC and sync EIC,
70 * The debounce EIC is used to capture the input signals' stable status
71 * (millisecond resolution) and a single-trigger mechanism is introduced
72 * into this sub-module to enhance the input event detection reliability.
[all …]
|
| D | gpio-pmic-eic-sprd.c | 1 // SPDX-License-Identifier: GPL-2.0
15 /* EIC registers definition */
27 * The PMIC EIC controller only has one bank, and each bank now can contain
33 #define SPRD_PMIC_EIC_BIT(x) ((x) & (SPRD_PMIC_EIC_PER_BANK_NR - 1))
48 * struct sprd_pmic_eic - PMIC EIC controller
51 * @offset: the EIC controller's offset address of the PMIC.
52 * @reg: the array to cache the EIC registers.
53 * @buslock: for bus lock/sync and unlock.
54 * @irq: the interrupt number of the PMIC EIC conteroller.
71 regmap_update_bits(pmic_eic->map, pmic_eic->offset + reg, in sprd_pmic_eic_update()
[all …]
|
| /linux-6.14.4/arch/arm64/boot/dts/sprd/ |
| D | whale2.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/clock/sprd,sc9860-clk.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 compatible = "simple-bus";
17 #address-cells = <2>;
18 #size-cells = <2>;
66 ap-apb@70000000 {
67 compatible = "simple-bus";
[all …]
|
| /linux-6.14.4/drivers/irqchip/ |
| D | irq-mips-gic.c | 6 * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
10 #define pr_fmt(fmt) "irq-mips-gic: " fmt
26 #include <asm/mips-cps.h>
30 #include <dt-bindings/interrupt-controller/mips-gic.h>
44 #define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE)
47 #define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE)
98 * for_each_online_cpu_gic() - Iterate over online CPUs, access local registers
109 for ((cpu) = __gic_with_next_online_cpu(-1); \
115 * gic_irq_lock_cluster() - Lock redirect block access to IRQ's cluster
163 /* All local interrupts are routable in EIC mode. */ in gic_local_irq_is_routable()
[all …]
|
| /linux-6.14.4/ |
| D | MAINTAINERS | 5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-[email protected]
88 F: drivers/scsi/3w-*
[all …]
|