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/linux-6.14.4/drivers/gpu/drm/bridge/
Dnwl-dsi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * i.MX8 NWL MIPI DSI host driver
15 #include <linux/media-bus-format.h>
34 #include "nwl-dsi.h"
36 #define DRV_NAME "nwl-dsi"
77 * The DSI host controller needs this reset sequence according to NWL:
78 * 1. Deassert pclk reset to get access to DSI regs
79 * 2. Configure DSI Host and DPHY and enable DPHY
80 * 3. Deassert ESC and BYTE resets to allow host TX operations)
81 * 4. Send DSI cmds to configure peripheral (handled by panel drv)
[all …]
Dsamsung-dsim.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include <linux/media-bus-format.h>
25 #include <drm/bridge/samsung-dsim.h>
33 #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) argument
43 #define DSIM_LPDR_TIMEOUT(x) ((x) << 0) argument
44 #define DSIM_BTA_TIMEOUT(x) ((x) << 16) argument
47 #define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0) argument
50 #define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20) argument
53 #define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25) argument
61 #define DSIM_LANE_EN(x) (((x) & 0xf) << 1) argument
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Dti-sn65dsi83.c1 // SPDX-License-Identifier: GPL-2.0
6 * - SN65DSI83
7 * = 1x Single-link DSI ~ 1x Single-link LVDS
8 * - Supported
9 * - Single-link LVDS mode tested
10 * - SN65DSI84
11 * = 1x Single-link DSI ~ 2x Single-link or 1x Dual-link LVDS
12 * - Supported
13 * - Dual-link LVDS mode tested
14 * - 2x Single-link LVDS mode unsupported
[all …]
Dtc358775.c1 // SPDX-License-Identifier: GPL-2.0
3 * TC358775 DSI to LVDS bridge driver
16 #include <linux/media-bus-format.h>
36 /* DSI D-PHY Layer Registers */
51 /* DSI PPI Layer Registers */
52 #define PPI_STARTPPI 0x0104 /* START control bit of PPI-TX function. */
59 #define PPI_TX_RX_TA 0x013C /* DSI Bus Turn Around timing parameters */
93 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX function */
106 #define DSIERRCNT 0x0300 /* DSI Error Count */
120 #define LV_MX0003 0x0480 /* Bit 0 to 3 */
[all …]
Dchipone-icn6211.c1 // SPDX-License-Identifier: GPL-2.0+
18 #include <linux/media-bus-format.h>
150 struct mipi_dsi_device *dsi; member
208 struct mipi_dsi_device *dsi = context; in chipone_dsi_read() local
212 ret = mipi_dsi_generic_read(dsi, &reg16, 2, val, val_size); in chipone_dsi_read()
214 return ret == val_size ? 0 : -EINVAL; in chipone_dsi_read()
219 struct mipi_dsi_device *dsi = context; in chipone_dsi_write() local
221 return mipi_dsi_generic_write(dsi, data, 2); in chipone_dsi_write()
240 ret = regmap_read(icn->regmap, reg, &pval); in chipone_readb()
247 return regmap_write(icn->regmap, reg, val); in chipone_writeb()
[all …]
Dlontium-lt9211.c1 // SPDX-License-Identifier: GPL-2.0
6 * 2xDSI/2xLVDS/1xDPI -> 2xDSI/2xLVDS/1xDPI
8 * 1xDSI -> 1xLVDS
17 #include <linux/media-bus-format.h>
40 /* DSI lane count - 0 means 4 lanes ; 1, 2, 3 means 1, 2, 3 lanes. */
47 struct mipi_dsi_device *dsi; member
106 return drm_bridge_attach(bridge->encoder, ctx->panel_bridge, in lt9211_attach()
107 &ctx->bridge, flags); in lt9211_attach()
116 ret = regmap_bulk_read(ctx->regmap, REG_CHIPID0, chipid, 3); in lt9211_read_chipid()
118 dev_err(ctx->dev, "Failed to read Chip ID: %d\n", ret); in lt9211_read_chipid()
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Dtc358764.c1 // SPDX-License-Identifier: GPL-2.0
24 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
38 /* DSI layer registers */
39 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
68 #define LV_MX0003 0x0480 /* Mux input bit 0 to 3 */
69 #define LV_MX0407 0x0484 /* Mux input bit 4 to 7 */
70 #define LV_MX0811 0x0488 /* Mux input bit 8 to 11 */
71 #define LV_MX1215 0x048C /* Mux input bit 12 to 15 */
72 #define LV_MX1619 0x0490 /* Mux input bit 16 to 19 */
73 #define LV_MX2023 0x0494 /* Mux input bit 20 to 23 */
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Dti-dlpc3433.c1 // SPDX-License-Identifier: GPL-2.0+
19 #include <linux/media-bus-format.h>
34 WR_DSI_HS_CLK = 0xBD, /* Write DSI HS Clock */
36 WR_DSI_PORT_EN = 0xD7, /* Write DSI Port Enable */
60 struct mipi_dsi_device *dsi; member
111 struct device *dev = dlpc->dev; in dlpc_atomic_enable()
112 struct drm_display_mode *mode = &dlpc->mode; in dlpc_atomic_enable()
113 struct regmap *regmap = dlpc->regmap; in dlpc_atomic_enable()
120 DRM_DEV_DEBUG(dev, "DLPC3433 device id: 0x%02x\n", devid); in dlpc_atomic_enable()
123 DRM_DEV_ERROR(dev, "Unsupported DLPC device id: 0x%02x\n", devid); in dlpc_atomic_enable()
[all …]
/linux-6.14.4/drivers/gpu/drm/bridge/cadence/
Dcdns-dsi-core.c1 // SPDX-License-Identifier: GPL-2.0
23 #include <linux/phy/phy-mipi-dphy.h>
25 #include "cdns-dsi-core.h"
27 #include "cdns-dsi-j721e.h"
31 #define SP_HS_FIFO_DEPTH(x) (((x) & GENMASK(30, 26)) >> 26) argument
32 #define SP_LP_FIFO_DEPTH(x) (((x) & GENMASK(25, 21)) >> 21) argument
33 #define VRS_FIFO_DEPTH(x) (((x) & GENMASK(20, 16)) >> 16) argument
34 #define DIRCMD_FIFO_DEPTH(x) (((x) & GENMASK(15, 13)) >> 13) argument
39 #define INTERNAL_DATAPATH_SIZE ((x) & GENMASK(11, 10))
40 #define NUM_IFACE(x) ((((x) & GENMASK(9, 8)) >> 8) + 1) argument
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/linux-6.14.4/drivers/gpu/drm/bridge/imx/
Dimx93-mipi-dsi.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <linux/media-bus-format.h>
17 #include <linux/phy/phy-mipi-dphy.h>
29 #define CFGCLKFREQRANGE(x) FIELD_PREP(CFGCLKFREQRANGE_MASK, (x)) argument
35 #define HSFREQRANGE(x) FIELD_PREP(HSFREQRANGE_MASK, (x)) argument
42 #define M(x) FIELD_PREP(M_MASK, ((x) - 2)) argument
44 #define N(x) FIELD_PREP(N_MASK, ((x) - 1)) argument
46 #define VCO_CTRL(x) FIELD_PREP(VCO_CTRL_MASK, (x)) argument
48 #define PROP_CTRL(x) FIELD_PREP(PROP_CTRL_MASK, (x)) argument
50 #define INT_CTRL(x) FIELD_PREP(INT_CTRL_MASK, (x)) argument
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/linux-6.14.4/drivers/gpu/drm/omapdrm/dss/
Ddsi.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #define DSS_SUBSYS_NAME "DSI"
48 #include "dsi.h"
50 #define REG_GET(dsi, idx, start, end) \ argument
51 FLD_GET(dsi_read_reg(dsi, idx), start, end)
53 #define REG_FLD_MOD(dsi, idx, val, start, end) \ argument
54 dsi_write_reg(dsi, idx, FLD_MOD(dsi_read_reg(dsi, idx), val, start, end))
56 static int dsi_init_dispc(struct dsi_data *dsi);
57 static void dsi_uninit_dispc(struct dsi_data *dsi);
59 static int dsi_vc_send_null(struct dsi_data *dsi, int vc, int channel);
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/linux-6.14.4/drivers/video/fbdev/omap2/omapfb/dss/
Ddsi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/video/omap2/dss/dsi.c
9 #define DSS_SUBSYS_NAME "DSI"
47 /* DSI Protocol Engine */
213 /* DSI PLL HSDIV indices */
408 return to_platform_device(dssdev->dev); in dsi_get_dsidev_from_dssdev()
429 return out ? to_platform_device(out->dev) : NULL; in dsi_get_dsidev_from_id()
435 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); in dsi_write_reg() local
439 case DSI_PROTO: base = dsi->proto_base; break; in dsi_write_reg()
440 case DSI_PHY: base = dsi->phy_base; break; in dsi_write_reg()
[all …]
/linux-6.14.4/drivers/gpu/drm/panel/
Dpanel-samsung-s6e63m0-dsi.c1 // SPDX-License-Identifier: GPL-2.0
3 * DSI interface to the Samsung S6E63M0 panel.
14 #include "panel-samsung-s6e63m0.h"
22 struct mipi_dsi_device *dsi = to_mipi_dsi_device(dev); in s6e63m0_dsi_dcs_read() local
25 ret = mipi_dsi_dcs_read(dsi, cmd, data, 1); in s6e63m0_dsi_dcs_read()
27 dev_err(dev, "could not read DCS CMD %02x\n", cmd); in s6e63m0_dsi_dcs_read()
31 dev_dbg(dev, "DSI read CMD %02x = %02x\n", cmd, *data); in s6e63m0_dsi_dcs_read()
39 struct mipi_dsi_device *dsi = to_mipi_dsi_device(dev); in s6e63m0_dsi_dcs_write() local
47 dev_dbg(dev, "DSI writing dcs seq: %*ph\n", (int)len, data); in s6e63m0_dsi_dcs_write()
53 remain = len - 1; in s6e63m0_dsi_dcs_write()
[all …]
Dpanel-novatek-nt35510.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * This display driver (and I refer to the physical component NT35510,
14 * the code needed to set up and configure the panel will be similar,
16 * per-panel, e.g. for physical size.
18 * This driver is for the DSI interface to panels using the NT35510.
22 * this panel driver should be refactored to also support that use
76 #define NT35510_DOPCTR_0_DSIM BIT(4) /* Enable video mode on DSI */
147 * struct nt35510_config - the display-specific NT35510 configuration
156 * not linearly placed along the X axis, we get points 0, 1, 3, 5
173 * +------------------------------------------->
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Dpanel-novatek-nt35560.c1 // SPDX-License-Identifier: GPL-2.0+
3 * MIPI-DSI Novatek NT35560-based panel controller.
6 * Sony ACX424AKM - a 480x854 AMOLED DSI panel
7 * Sony ACX424AKP - a 480x864 AMOLED DSI panel
9 * Copyright (C) Linaro Ltd. 2019-2021
11 * Based on code and know-how from Marcus Lorentzon
12 * Copyright (C) ST-Ericsson SA 2010
13 * Based on code and know-how from Johan Olson and Joakim Wesslen
35 * Sony seems to use vendor ID 0x81
151 struct mipi_dsi_device *dsi = to_mipi_dsi_device(nt->dev); in nt35560_set_brightness() local
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Dpanel-dsi-cm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Generic DSI Command Mode panel driver
5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
44 struct mipi_dsi_device *dsi; member
81 if (ddata->bldev) in dsicm_bl_power()
82 backlight = ddata->bldev; in dsicm_bl_power()
83 else if (ddata->extbldev) in dsicm_bl_power()
84 backlight = ddata->extbldev; in dsicm_bl_power()
96 ddata->hw_guard_wait = msecs_to_jiffies(guard_msec); in hw_guard_start()
97 ddata->hw_guard_end = jiffies + ddata->hw_guard_wait; in hw_guard_start()
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Dpanel-sharp-lq101r1sx01.c1 // SPDX-License-Identifier: GPL-2.0-only
21 /* the datasheet refers to them as DSI-LINK1 and DSI-LINK2 */
37 unsigned int refresh = drm_mode_vrefresh(sharp->mode); in sharp_wait_frames()
48 struct mipi_dsi_device *dsi = sharp->link1; in sharp_panel_write() local
51 err = mipi_dsi_generic_write(dsi, payload, sizeof(payload)); in sharp_panel_write()
53 dev_err(&dsi->dev, "failed to write %02x to %04x: %zd\n", in sharp_panel_write()
58 err = mipi_dsi_dcs_nop(dsi); in sharp_panel_write()
60 dev_err(&dsi->dev, "failed to send DCS nop: %zd\n", err); in sharp_panel_write()
76 err = mipi_dsi_generic_read(sharp->link1, &offset, sizeof(offset), in sharp_panel_read()
79 dev_err(&sharp->link1->dev, "failed to read from %04x: %zd\n", in sharp_panel_read()
[all …]
/linux-6.14.4/drivers/gpu/drm/sprd/
Dsprd_dsi.c1 // SPDX-License-Identifier: GPL-2.0
139 return (readl(ctx->base + offset) & mask) >> shift; in dsi_reg_rd()
148 ret = readl(ctx->base + offset); in dsi_reg_wr()
151 writel(ret, ctx->base + offset); in dsi_reg_wr()
158 u32 ret = readl(ctx->base + offset); in dsi_reg_up()
160 writel((ret & ~mask) | (val & mask), ctx->base + offset); in dsi_reg_up()
165 struct sprd_dsi *dsi = context; in regmap_tst_io_write() local
166 struct dsi_context *ctx = &dsi->ctx; in regmap_tst_io_write()
169 return -EINVAL; in regmap_tst_io_write()
171 drm_dbg(dsi->drm, "reg = 0x%02x, val = 0x%02x\n", reg, val); in regmap_tst_io_write()
[all …]
/linux-6.14.4/drivers/video/fbdev/omap2/omapfb/displays/
Dpanel-dsi-cm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Generic DSI Command Mode panel driver
28 /* DSI Virtual channel. Hardcoded for now. */
92 ddata->hw_guard_wait = msecs_to_jiffies(guard_msec); in hw_guard_start()
93 ddata->hw_guard_end = jiffies + ddata->hw_guard_wait; in hw_guard_start()
98 unsigned long wait = ddata->hw_guard_end - jiffies; in hw_guard_wait()
100 if ((long)wait > 0 && time_before_eq(wait, ddata->hw_guard_wait)) { in hw_guard_wait()
108 struct omap_dss_device *in = ddata->in; in dsicm_dcs_read_1()
112 r = in->ops.dsi->dcs_read(in, ddata->channel, dcs_cmd, buf, 1); in dsicm_dcs_read_1()
124 struct omap_dss_device *in = ddata->in; in dsicm_dcs_write_0()
[all …]
/linux-6.14.4/drivers/gpu/drm/renesas/rcar-du/
Drcar_mipi_dsi.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car MIPI DSI Encoder
70 struct clk *dsi; member
176 static void rcar_mipi_dsi_write(struct rcar_mipi_dsi *dsi, u32 reg, u32 data) in rcar_mipi_dsi_write() argument
178 iowrite32(data, dsi->mmio + reg); in rcar_mipi_dsi_write()
181 static u32 rcar_mipi_dsi_read(struct rcar_mipi_dsi *dsi, u32 reg) in rcar_mipi_dsi_read() argument
183 return ioread32(dsi->mmio + reg); in rcar_mipi_dsi_read()
186 static void rcar_mipi_dsi_clr(struct rcar_mipi_dsi *dsi, u32 reg, u32 clr) in rcar_mipi_dsi_clr() argument
188 rcar_mipi_dsi_write(dsi, reg, rcar_mipi_dsi_read(dsi, reg) & ~clr); in rcar_mipi_dsi_clr()
191 static void rcar_mipi_dsi_set(struct rcar_mipi_dsi *dsi, u32 reg, u32 set) in rcar_mipi_dsi_set() argument
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/linux-6.14.4/drivers/gpu/drm/vc4/
Dvc4_dsi.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * BCM2835 contains two DSI modules, DSI0 and DSI1. DSI0 is a
10 * single-lane DSI controller, while DSI1 is a more modern 4-lane DSI
16 * This driver has been tested for DSI1 video-mode display only
21 #include <linux/clk-provider.h>
25 #include <linux/dma-mapping.h>
81 /* Trigger according to TRIG_CMD */
146 * of going to LP-STOP.
149 /* Transmit blanking packet only during vblank, instead of allowing LP-STOP. */
151 /* Transmit blanking packet only during HFP, instead of allowing LP-STOP. */
[all …]
/linux-6.14.4/drivers/gpu/drm/mediatek/
Dmtk_dsi.c1 // SPDX-License-Identifier: GPL-2.0-only
238 static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data) in mtk_dsi_mask() argument
240 u32 temp = readl(dsi->regs + offset); in mtk_dsi_mask()
242 writel((temp & ~mask) | (data & mask), dsi->regs + offset); in mtk_dsi_mask()
245 static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi) in mtk_dsi_phy_timconfig() argument
248 u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, HZ_PER_MHZ); in mtk_dsi_phy_timconfig()
249 struct mtk_phy_timing *timing = &dsi->phy_timing; in mtk_dsi_phy_timconfig()
251 timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1; in mtk_dsi_phy_timconfig()
252 timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000; in mtk_dsi_phy_timconfig()
253 timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 - in mtk_dsi_phy_timconfig()
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/linux-6.14.4/Documentation/devicetree/bindings/display/bridge/
Dti,sn65dsi83.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SN65DSI83 and SN65DSI84 DSI to LVDS bridge chip
10 - Marek Vasut <[email protected]>
13 Texas Instruments SN65DSI83 1x Single-link MIPI DSI
14 to 1x Single-link LVDS
16 Texas Instruments SN65DSI84 1x Single-link MIPI DSI
17 to 1x Dual-link or 2x Single-link LVDS
23 - ti,sn65dsi83
[all …]
/linux-6.14.4/drivers/gpu/drm/msm/dsi/phy/
Ddsi_phy_10nm.c2 * SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
11 #include "dsi.xml.h"
15 * DSI PLL 10nm - clock diagram (eg: DSI0):
20 * +---------+ | +----------+ | +----+
21 * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk
22 * +---------+ | +----------+ | +----+
26 * | | +----+ | |\ dsi0_pclk_mux
27 * | |--| /2 |--o--| \ |
28 * | | +----+ | \ | +---------+
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek DSI Controller
10 - Chun-Kuang Hu <[email protected]>
11 - Philipp Zabel <[email protected]>
12 - Jitao Shi <[email protected]>
15 The MediaTek DSI function block is a sink of the display subsystem and can
16 drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
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