Searched +full:cortex +full:- +full:r5 (Results 1 – 21 of 21) sorted by relevance
/linux-6.14.4/arch/arm/mm/ |
D | proc-v7m.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 3 * linux/arch/arm/mm/proc-v7m.S 8 * This is the "shell" of the ARMv7-M processor support. 15 #include "proc-macros.S" 32 * - loc - location to jump to for soft reset 105 * This should be able to cover all ARMv7-M cores. 117 ldr r5, [r0, #V7M_SCB_SHCSR] 118 orr r5, #(V7M_SCB_SHCSR_USGFAULTENA | V7M_SCB_SHCSR_BUSFAULTENA | V7M_SCB_SHCSR_MEMFAULTENA) 119 str r5, [r0, #V7M_SCB_SHCSR] 122 mov r5, #0x80000000 [all …]
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D | proc-v7.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 3 * linux/arch/arm/mm/proc-v7.S 9 #include <linux/arm-smccc.h> 15 #include <asm/asm-offsets.h> 17 #include <asm/pgtable-hwdef.h> 20 #include "proc-macros.S" 23 #include "proc-v7-3level.S" 25 #include "proc-v7-2level.S" 28 .arch armv7-a 49 * - loc - location to jump to for soft reset [all …]
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D | cache-v7.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 3 * linux/arch/arm/mm/cache-v7.S 16 #include <asm/hardware/cache-b15-rac.h> 18 #include "proc-macros.S" 20 .arch armv7-a 52 mov r3, r3, lsl r1 @ NumWays-1 shifted into bits [31:...] 65 subs r0, r0, #1 @ Set-- 67 subs r3, r3, r1 @ Way-- 69 mrc p15, 1, r0, c0, c0, 0 @ re-read cache geometry from CCSIDR 79 * Flush the whole I-cache. [all …]
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/linux-6.14.4/arch/arm64/boot/dts/ti/ |
D | k3-j722s.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT 5 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/interrupt-controller/irq.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/soc/ti,sci_pm_domain.h> 13 #include "k3-pinctrl.h" 18 interrupt-parent = <&gic500>; 19 #address-cells = <2>; 20 #size-cells = <2>; [all …]
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D | k3-am62a.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT 5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/interrupt-controller/irq.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/soc/ti,sci_pm_domain.h> 13 #include "k3-pinctrl.h" 18 interrupt-parent = <&gic500>; 19 #address-cells = <2>; 20 #size-cells = <2>; [all …]
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D | k3-am62p.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT 5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/interrupt-controller/irq.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/soc/ti,sci_pm_domain.h> 13 #include "k3-pinctrl.h" 18 interrupt-parent = <&gic500>; 19 #address-cells = <2>; 20 #size-cells = <2>; [all …]
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/linux-6.14.4/arch/arm/kernel/ |
D | entry-header.S | 1 /* SPDX-License-Identifier: GPL-2.0 */ 6 #include <asm/asm-offsets.h> 9 #include <asm/uaccess-asm.h> 13 @ ----------------- 59 * ARMv7-M exception entry/exit macros. 86 @ we cannot rely on r0-r3 and r12 matching the value saved in the 87 @ exception frame because of tail-chaining. So these have to be 89 ldmia r12!, {r0-r3} 94 sub sp, #PT_REGS_SIZE-S_IP 95 stmdb sp!, {r0-r11} [all …]
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D | head.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 5 * Copyright (C) 1994-2002 Russell King 9 * Kernel startup code for all 32-bit CPUs 19 #include <asm/asm-offsets.h> 48 .equ swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE 74 * --------------------------- 77 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0, 83 * See linux/arch/arm/tools/mach-types for the complete list of machine 87 * crap here - that's what the boot loader (or in extreme, well justified 97 THUMB( bx r9 ) @ If this is a Thumb-2 kernel, [all …]
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/linux-6.14.4/arch/arm/crypto/ |
D | sha1-armv4-large.S | 2 @ SPDX-License-Identifier: GPL-2.0 23 @ Size/performance trade-off 28 @ armv4-small 392/+29% 1958/+64% 2250/+96% 29 @ armv4-compact 740/+89% 1552/+26% 1840/+22% 30 @ armv4-large 1420/+92% 1307/+19% 1370/+34%[***] 42 @ i-cache availability, branch penalties, etc. 49 @ [***] which is also ~35% better than compiler generated code. Dual- 50 @ issue Cortex A8 core was measured to process input block in 55 @ Rescheduling for dual-issue pipeline resulted in 13% improvement on 56 @ Cortex A8 core and in absolute terms ~870 cycles per input block [all …]
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D | aes-ce-core.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 3 * aes-ce-core.S - AES in CBC/CTR/XTS mode using ARMv8 Crypto Extensions 12 .arch armv8-a 13 .fpu crypto-neon-fp-armv8 102 vld1.32 {q10-q11}, [ip]! 104 vld1.32 {q12-q13}, [ip]! 106 vld1.32 {q10-q11}, [ip]! 108 vld1.32 {q12-q13}, [ip]! 110 blo 0f @ AES-128: 10 rounds 111 vld1.32 {q10-q11}, [ip]! [all …]
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D | poly1305-armv4.pl | 2 # SPDX-License-Identifier: GPL-1.0+ OR BSD-3-Clause 5 # Written by Andy Polyakov, @dot-asm, initially for the OpenSSL 9 # IALU(*)/gcc-4.4 NEON 11 # ARM11xx(ARMv6) 7.78/+100% - 12 # Cortex-A5 6.35/+130% 3.00 13 # Cortex-A8 6.25/+115% 2.36 14 # Cortex-A9 5.10/+95% 2.55 15 # Cortex-A15 3.85/+85% 1.25(**) 18 # (*) this is for -march=armv6, i.e. with bunch of ldrb loading data; 19 # (**) these are trade-off results, they can be improved by ~8% but at [all …]
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D | blake2b-neon-core.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 23 ROR16_TABLE .req r5 29 // M_0-M_3 are occasionally used for other purposes too. 50 // rotation amounts with NEON. (On Cortex-A53 it's the same speed as 51 // vshr.u64 + vsli.u64, while on Cortex-A7 it's faster.) 64 // NEON registers q0-q7. The message block is in q8..q15 (M_0-M_15). The stack 65 // pointer points to a 32-byte aligned buffer containing a copy of q8 and q9 66 // (M_0-M_3), so that they can be reloaded if they are used as temporary 67 // registers. The macro arguments s0-s15 give the order in which the message 135 // registers. Use q8-q9 (M_0-M_3) for this, and reload them afterwards. [all …]
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D | sha512-armv4.pl | 2 # SPDX-License-Identifier: GPL-2.0 22 # by gcc 3.4 and it spends ~72 clock cycles per byte [on single-issue 27 # Rescheduling for dual-issue pipeline resulted in 6% improvement on 28 # Cortex A8 core and ~40 cycles per processed byte. 32 # Profiler-assisted and platform-specific optimization resulted in 7% 37 # Add NEON implementation. On Cortex A8 it was measured to process 38 # one byte in 23.3 cycles or ~60% faster than integer-only code. 44 # Technical writers asserted that 3-way S4 pipeline can sustain 46 # not be observed, see https://www.openssl.org/~appro/Snapdragon-S4.html 47 # for further details. On side note Cortex-A15 processes one byte in [all …]
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D | sha256-armv4.pl | 2 # SPDX-License-Identifier: GPL-2.0 21 # Performance is ~2x better than gcc 3.4 generated code and in "abso- 22 # lute" terms is ~2250 cycles per 64-byte block or ~35 cycles per 23 # byte [on single-issue Xscale PXA250 core]. 27 # Rescheduling for dual-issue pipeline resulted in 22% improvement on 28 # Cortex A8 core and ~20 cycles per processed byte. 32 # Profiler-assisted and platform-specific optimization resulted in 16% 33 # improvement on Cortex A8 core and ~15.4 cycles per processed byte. 37 # Add NEON implementation. On Cortex A8 it was measured to process one 38 # byte in 12.5 cycles or 23% faster than integer-only code. Snapdragon [all …]
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/linux-6.14.4/arch/arm/mach-tegra/ |
D | reset-handler.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 13 #include <asm/asm-offsets.h> 22 .arch armv7-a 30 * re-enabling sdram. 74 /* L2 cache resume & re-enable */ 106 * r0=3 for the wake-up notification. 135 * must be position-independent. 147 ldr r5, [r12, #RESET_DATA(TF_PRESENT)] 148 cmp r5, #0 156 # Tegra20 is a Cortex-A9 r1p1 [all …]
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/linux-6.14.4/Documentation/devicetree/bindings/arm/ |
D | cpus.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Lorenzo Pieralisi <[email protected]> 21 with updates for 32-bit and 64-bit ARM systems provided in this document. 30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in 59 On 32-bit ARM v7 or later systems this property is 68 On ARM v8 64-bit systems this property is required 71 * If cpus node's #address-cells property is set to 2 79 * If cpus node's #address-cells property is set to 1 [all …]
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/linux-6.14.4/arch/arm/mach-exynos/ |
D | mcpm-exynos.c | 1 // SPDX-License-Identifier: GPL-2.0 5 // Based on arch/arm/mach-vexpress/dcscb.c 7 #include <linux/arm-cci.h> 12 #include <linux/soc/samsung/exynos-regs-pmu.h> 54 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", \ 65 return -EINVAL; in exynos_cpu_powerup() 71 * This assumes the cluster number of the big cores(Cortex A15) in exynos_cpu_powerup() 72 * is 0 and the Little cores(Cortex A7) is 1. in exynos_cpu_powerup() 87 timeout--; in exynos_cpu_powerup() 95 return -ETIMEDOUT; in exynos_cpu_powerup() [all …]
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/linux-6.14.4/drivers/remoteproc/ |
D | xlnx_r5_remoteproc.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * ZynqMP R5 Remote Processor driver 7 #include <dt-bindings/power/xlnx-zynqmp-power.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/firmware/xlnx-zynqmp.h> 12 #include <linux/mailbox/zynqmp-ipi-message.h> 34 * reflects possible values of xlnx,cluster-mode dt-property 38 LOCKSTEP_MODE = 1, /* cores execute same code in lockstep,clk-for-clk */ 43 * struct mem_bank_data - Memory Bank description 48 * @pm_domain_id: Power-domains id of memory bank for firmware to turn on/off [all …]
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/linux-6.14.4/Documentation/devicetree/bindings/arm/tegra/ |
D | nvidia,tegra194-cbb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Sumit Gupta <[email protected]> 15 multiple hierarchical sub-NOCs (Network-on-Chip) and connects various 20 "AON-NOC, SCE-NOC, RCE-NOC, BPMP-NOC, CV-NOC" and "CBB Central NOC" 28 - For CCPLEX (CPU Complex) initiator, the driver sets ERD bit. So, the 31 - For other initiators, the ERD is disabled. So, the access issuing 34 include all engines using Cortex-R5 (which is ARMv7 CPU cluster) and [all …]
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/linux-6.14.4/arch/arm/mach-omap2/ |
D | sleep44xx.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 13 #include <asm/hardware/cache-l2x0.h> 15 #include "omap-secure.h" 19 #include "omap4-sar-layout.h" 21 .arch armv7-a 46 * 0 - No context lost 47 * 1 - CPUx L1 and logic lost: MPUSS CSWR 48 * 2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR 49 * 3 - CPUx L1 and logic lost + GIC + L2 lost: MPUSS OFF 51 * Post WFI, CPU transitions to DORMANT or OFF power state and on wake-up [all …]
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/linux-6.14.4/arch/arm/ |
D | Kconfig.debug | 1 # SPDX-License-Identifier: GPL-2.0 44 once the kernel has booted up - it's a one time check. 104 1 - undefined instruction events 105 2 - system calls 106 4 - invalid data aborts 107 8 - SIGSEGV faults 108 16 - SIGBUS faults 112 bool "Kernel low-level debugging functions (read help!)" 125 prompt "Kernel low-level debugging port" 129 bool "Kernel low-level debugging messages via Alpine UART0" [all …]
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