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/linux-6.14.4/tools/testing/selftests/kvm/x86/
Ducna_injection_test.c79 uint64_t ctl2; in ucna_injection_guest_code() local
85 ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK)); in ucna_injection_guest_code()
86 wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 | MCI_CTL2_CMCI_EN); in ucna_injection_guest_code()
97 ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK)); in ucna_injection_guest_code()
98 wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 & ~MCI_CTL2_CMCI_EN); in ucna_injection_guest_code()
109 uint64_t ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK)); in cmci_disabled_guest_code() local
110 wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 | MCI_CTL2_CMCI_EN); in cmci_disabled_guest_code()
117 uint64_t ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK)); in cmci_enabled_guest_code() local
118 wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 | MCI_CTL2_RESERVED_BIT); in cmci_enabled_guest_code()
/linux-6.14.4/drivers/firmware/cirrus/test/
Dcs_dsp_test_control_parse.c984 struct cs_dsp_coeff_ctl *walkctl, *ctl1, *ctl2; in cs_dsp_ctl_parse_fw_name() local
1022 ctl2 = NULL; in cs_dsp_ctl_parse_fw_name()
1027 ctl2 = walkctl; in cs_dsp_ctl_parse_fw_name()
1031 KUNIT_EXPECT_NOT_NULL(test, ctl2); in cs_dsp_ctl_parse_fw_name()
1033 KUNIT_EXPECT_EQ(test, ctl2->offset, 2); in cs_dsp_ctl_parse_fw_name()
1042 struct cs_dsp_coeff_ctl *ctl1, *ctl2; in cs_dsp_ctl_alg_id_uniqueness() local
1066 ctl2 = list_next_entry(ctl1, list); in cs_dsp_ctl_alg_id_uniqueness()
1068 KUNIT_EXPECT_NOT_NULL(test, ctl2); in cs_dsp_ctl_alg_id_uniqueness()
1069 KUNIT_EXPECT_NE(test, ctl1->alg_region.alg, ctl2->alg_region.alg); in cs_dsp_ctl_alg_id_uniqueness()
1070 KUNIT_EXPECT_EQ(test, ctl1->alg_region.type, ctl2->alg_region.type); in cs_dsp_ctl_alg_id_uniqueness()
[all …]
/linux-6.14.4/drivers/gpu/drm/i915/display/
Dintel_backlight.c606 u32 ctl, ctl2, freq; in i965_enable_backlight() local
608 ctl2 = intel_de_read(i915, BLC_PWM_CTL2); in i965_enable_backlight()
609 if (ctl2 & BLM_PWM_ENABLE) { in i965_enable_backlight()
612 ctl2 &= ~BLM_PWM_ENABLE; in i965_enable_backlight()
613 intel_de_write(i915, BLC_PWM_CTL2, ctl2); in i965_enable_backlight()
623 ctl2 = BLM_PIPE(pipe); in i965_enable_backlight()
625 ctl2 |= BLM_COMBINATION_MODE; in i965_enable_backlight()
627 ctl2 |= BLM_POLARITY_I965; in i965_enable_backlight()
628 intel_de_write(i915, BLC_PWM_CTL2, ctl2); in i965_enable_backlight()
630 intel_de_write(i915, BLC_PWM_CTL2, ctl2 | BLM_PWM_ENABLE); in i965_enable_backlight()
[all …]
Ddvo_tfp410.c207 u8 ctl2; in tfp410_detect() local
209 if (tfp410_readb(dvo, TFP410_CTL_2, &ctl2)) { in tfp410_detect()
210 if (ctl2 & TFP410_CTL_2_RSEN) in tfp410_detect()
Dintel_backlight_regs.h79 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
/linux-6.14.4/drivers/mtd/nand/raw/
Dcafe_nand.c66 uint32_t ctl2; member
174 cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2); in cafe_nand_cmdfunc()
176 cafe->ctl2 &= ~(1<<30); in cafe_nand_cmdfunc()
243 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2); in cafe_nand_cmdfunc()
245 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2); in cafe_nand_cmdfunc()
248 cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n", in cafe_nand_cmdfunc()
298 WARN_ON(cafe->ctl2 & (1<<30)); in cafe_nand_cmdfunc()
310 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2); in cafe_nand_cmdfunc()
314 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2); in cafe_nand_cmdfunc()
544 cafe->ctl2 |= (1<<30); in cafe_nand_write_page_lowlevel()
[all …]
/linux-6.14.4/drivers/rtc/
Drtc-rs5c348.c79 txbuf[0] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */ in rs5c348_rtc_set_time()
81 txbuf[2] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */ in rs5c348_rtc_set_time()
124 txbuf[0] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */ in rs5c348_rtc_read_time()
126 txbuf[2] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */ in rs5c348_rtc_read_time()
Drtc-rzn1.c250 u32 subu = 0, ctl2; in rzn1_rtc_set_offset() local
284 ret = readl_poll_timeout(rtc->base + RZN1_RTC_CTL2, ctl2, in rzn1_rtc_set_offset()
285 !(ctl2 & RZN1_RTC_CTL2_WUST), 100, 2000000); in rzn1_rtc_set_offset()
/linux-6.14.4/drivers/hwmon/
Dlm93.c291 * The two PWM CTL2 registers can read something other than what was
1752 u8 ctl2, ctl4; in pwm_show() local
1755 ctl2 = data->block9[nr][LM93_PWM_CTL2]; in pwm_show()
1757 if (ctl2 & 0x01) /* show user commanded value if enabled */ in pwm_show()
1760 rc = LM93_PWM_FROM_REG(ctl2 >> 4, (ctl4 & 0x07) ? in pwm_show()
1771 u8 ctl2, ctl4; in pwm_store() local
1780 ctl2 = lm93_read_byte(client, LM93_REG_PWM_CTL(nr, LM93_PWM_CTL2)); in pwm_store()
1782 ctl2 = (ctl2 & 0x0f) | LM93_PWM_TO_REG(val, (ctl4 & 0x07) ? in pwm_store()
1785 data->pwm_override[nr] = LM93_PWM_FROM_REG(ctl2 >> 4, in pwm_store()
1788 lm93_write_byte(client, LM93_REG_PWM_CTL(nr, LM93_PWM_CTL2), ctl2); in pwm_store()
[all …]
/linux-6.14.4/drivers/video/fbdev/
Darcfb.c394 unsigned char ctl2; in arcfb_ioctl() local
396 ctl2 = ks108_readb_ctl2(info->par); in arcfb_ioctl()
397 if (copy_to_user(argp, &ctl2, sizeof(ctl2))) in arcfb_ioctl()
/linux-6.14.4/drivers/net/
Dsungem_phy.c795 u16 ctl, ctl2; in marvell_setup_forced() local
825 ctl2 = sungem_phy_read(phy, MII_M1011_PHY_SPEC_CONTROL); in marvell_setup_forced()
826 ctl2 &= ~(MII_M1011_PHY_SPEC_CONTROL_MANUAL_MDIX | in marvell_setup_forced()
831 ctl2 |= (fd == DUPLEX_FULL) ? in marvell_setup_forced()
834 sungem_phy_write(phy, MII_1000BASETCONTROL, ctl2); in marvell_setup_forced()
/linux-6.14.4/drivers/net/ethernet/aquantia/atlantic/hw_atl/
Dhw_atl_a0.c455 txd->ctl2 = 0; in hw_atl_a0_hw_ring_tx_xmit()
465 txd->ctl2 |= (buff->mss << 16) | in hw_atl_a0_hw_ring_tx_xmit()
484 txd->ctl2 |= HW_ATL_A0_TXD_CTL2_LEN & (pkt_len << 14); in hw_atl_a0_hw_ring_tx_xmit()
488 txd->ctl2 |= HW_ATL_A0_TXD_CTL2_CTX_EN; in hw_atl_a0_hw_ring_tx_xmit()
Dhw_atl_b0.c679 txd->ctl2 = 0; in hw_atl_b0_hw_ring_tx_xmit()
690 txd->ctl2 |= (buff->mss << 16); in hw_atl_b0_hw_ring_tx_xmit()
698 txd->ctl2 |= (buff->len_l4 << 8) | in hw_atl_b0_hw_ring_tx_xmit()
715 txd->ctl2 |= HW_ATL_B0_TXD_CTL2_LEN & (pkt_len << 14); in hw_atl_b0_hw_ring_tx_xmit()
719 txd->ctl2 |= HW_ATL_B0_TXD_CTL2_CTX_EN; in hw_atl_b0_hw_ring_tx_xmit()
Dhw_atl_utils.h21 u32 ctl2; /* 63..46 - payload length, 45 - ctx enable, 44 - ctx index */ member
/linux-6.14.4/drivers/pci/pcie/
Daspm.c641 u32 ctl1 = 0, ctl2 = 0; in aspm_calc_l12_info() local
658 ctl2 |= FIELD_PREP(PCI_L1SS_CTL2_T_PWR_ON_SCALE, scale1) | in aspm_calc_l12_info()
662 ctl2 |= FIELD_PREP(PCI_L1SS_CTL2_T_PWR_ON_SCALE, scale2) | in aspm_calc_l12_info()
690 ctl2 == pctl2 && ctl2 == cctl2) in aspm_calc_l12_info()
707 pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, ctl2); in aspm_calc_l12_info()
708 pci_write_config_dword(child, child->l1ss + PCI_L1SS_CTL2, ctl2); in aspm_calc_l12_info()
/linux-6.14.4/drivers/dma/
Dpch_dma.c183 val = dma_readl(pd, CTL2); in pdc_enable_irq()
190 dma_writel(pd, CTL2, val); in pdc_enable_irq()
741 pd->regs.dma_ctl2 = dma_readl(pd, CTL2); in pch_dma_save_regs()
764 dma_writel(pd, CTL2, pd->regs.dma_ctl2); in pch_dma_restore_regs()
/linux-6.14.4/Documentation/devicetree/bindings/display/
Dlvds-data-mapping.yaml110 CTL2: Data Enable
/linux-6.14.4/drivers/net/wireless/mediatek/mt76/
Dmt76x02_mac.h145 u8 ctl2; member
/linux-6.14.4/drivers/net/wireless/ath/ath9k/
Dmac.h283 u32 ctl2; member
321 #define ds_ctl2 u.tx.ctl2
/linux-6.14.4/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra186-pmc.yaml117 hdmi-dp0, hdmi-dp1, pex-cntrl, pex-ctl2, pex-l0-rst,
/linux-6.14.4/drivers/infiniband/hw/bnxt_re/
Dqplib_res.c957 u16 ctl2; in bnxt_qplib_determine_atomics() local
967 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &ctl2); in bnxt_qplib_determine_atomics()
968 return !(ctl2 & PCI_EXP_DEVCTL2_ATOMIC_REQ); in bnxt_qplib_determine_atomics()
/linux-6.14.4/sound/soc/codecs/
Dcs35l33.h25 #define CS35L33_BST_CTL2 0x0C /* Boost Converter CTL2 */
Dcs35l35.h28 #define CS35L35_SP_FMT_CTL2 0x0E /* Serial Port Format CTL2 */
/linux-6.14.4/sound/mips/
Dhal2.h141 /* Bits in CTL2 register */
/linux-6.14.4/drivers/net/ethernet/marvell/octeontx2/af/
Drvu_cpt.c957 u64 ctl, ctl2; in rvu_mbox_handler_cpt_lf_reset() local
970 ctl2 = rvu_read64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf)); in rvu_mbox_handler_cpt_lf_reset()
978 rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf), ctl2); in rvu_mbox_handler_cpt_lf_reset()

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