| /linux-6.14.4/Documentation/devicetree/bindings/power/ |
| D | mediatek,power-controller.yaml | 163 clocks = <&topckgen CLK_TOP_MM_SEL>;
169 clocks = <&topckgen CLK_TOP_MM_SEL>,
176 clocks = <&topckgen CLK_TOP_MM_SEL>;
182 clocks = <&topckgen CLK_TOP_MM_SEL>;
189 clocks = <&topckgen CLK_TOP_MM_SEL>,
|
| /linux-6.14.4/include/dt-bindings/clock/ |
| D | mediatek,mt6735-topckgen.h | 52 #define CLK_TOP_MM_SEL 44 macro
|
| D | mediatek,mt6795-clk.h | 93 #define CLK_TOP_MM_SEL 82 macro
|
| D | mt8173-clk.h | 95 #define CLK_TOP_MM_SEL 85 macro
|
| D | mt6765-clk.h | 133 #define CLK_TOP_MM_SEL 98 macro
|
| D | mediatek,mt8365-clk.h | 73 #define CLK_TOP_MM_SEL 63 macro
|
| D | mt2712-clk.h | 132 #define CLK_TOP_MM_SEL 101 macro
|
| D | mt2701-clk.h | 87 #define CLK_TOP_MM_SEL 76 macro
|
| /linux-6.14.4/arch/arm64/boot/dts/mediatek/ |
| D | mt6795.dtsi | 304 clocks = <&topckgen CLK_TOP_MM_SEL>;
310 clocks = <&topckgen CLK_TOP_MM_SEL>,
317 clocks = <&topckgen CLK_TOP_MM_SEL>;
324 clocks = <&topckgen CLK_TOP_MM_SEL>;
332 clocks = <&topckgen CLK_TOP_MM_SEL>,
723 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
|
| D | mt8173.dtsi | 459 clocks = <&topckgen CLK_TOP_MM_SEL>;
465 clocks = <&topckgen CLK_TOP_MM_SEL>,
472 clocks = <&topckgen CLK_TOP_MM_SEL>;
478 clocks = <&topckgen CLK_TOP_MM_SEL>;
485 clocks = <&topckgen CLK_TOP_MM_SEL>,
1000 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
|
| D | mt8365.dtsi | 318 clocks = <&topckgen CLK_TOP_MM_SEL>,
|
| D | mt2712e.dtsi | 285 clocks = <&topckgen CLK_TOP_MM_SEL>,
|
| /linux-6.14.4/Documentation/devicetree/bindings/soc/mediatek/ |
| D | scpsys.txt | 68 <&topckgen CLK_TOP_MM_SEL>;
|
| /linux-6.14.4/drivers/clk/mediatek/ |
| D | clk-mt6735-topckgen.c | 338 …MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_sel_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0…
|
| D | clk-mt6795-topckgen.c | 458 TOP_MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x40, 24, 3, 31, 0),
|
| D | clk-mt8173-topckgen.c | 537 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x0040, 24, 4, 31),
|
| D | clk-mt8365.c | 415 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x040, 0x044,
|
| D | clk-mt2712.c | 648 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x040, 24, 3, 31),
|
| D | clk-mt2701.c | 493 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents,
|
| D | clk-mt6765.c | 376 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, CLK_CFG_0,
|
| /linux-6.14.4/arch/arm/boot/dts/mediatek/ |
| D | mt2701.dtsi | 156 clocks = <&topckgen CLK_TOP_MM_SEL>,
|
| D | mt7623.dtsi | 277 clocks = <&topckgen CLK_TOP_MM_SEL>,
|