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Searched full:clk_top_aud_48k_timing (Results 1 – 5 of 5) sorted by relevance

/linux-6.14.4/Documentation/devicetree/bindings/arm/mediatek/
Dmediatek,audsys.yaml77 <&topckgen CLK_TOP_AUD_48K_TIMING>,
/linux-6.14.4/include/dt-bindings/clock/
Dmt2701-clk.h157 #define CLK_TOP_AUD_48K_TIMING 146 macro
/linux-6.14.4/arch/arm/boot/dts/mediatek/
Dmt2701.dtsi437 <&topckgen CLK_TOP_AUD_48K_TIMING>,
Dmt7623.dtsi638 <&topckgen CLK_TOP_AUD_48K_TIMING>,
/linux-6.14.4/drivers/clk/mediatek/
Dclk-mt2701.c641 GATE_TOP_AUD(CLK_TOP_AUD_48K_TIMING, "a1sys_hp_ck", "aud_mux1_div",