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/linux-6.14.4/Documentation/devicetree/bindings/media/
Dmediatek,vcodec-decoder.yaml178 <&apmixedsys CLK_APMIXED_VENCPLL>,
193 <&apmixedsys CLK_APMIXED_VENCPLL>;
/linux-6.14.4/include/dt-bindings/clock/
Dmediatek,mt6735-apmixedsys.h11 #define CLK_APMIXED_VENCPLL 5 macro
Dmediatek,mt6795-clk.h146 #define CLK_APMIXED_VENCPLL 5 macro
Dmt8173-clk.h162 #define CLK_APMIXED_VENCPLL 7 macro
Dmt2712-clk.h15 #define CLK_APMIXED_VENCPLL 3 macro
/linux-6.14.4/drivers/clk/mediatek/
Dclk-mt6795-apmixedsys.c55 PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0, 0, 21, 0x260, 4, 0x0, 0x264, 0),
108 FH(CLK_APMIXED_VENCPLL, FH_VENCPLL, 0xb0),
Dclk-mt8173-apmixedsys.c72 PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0, 0, 21, 0x260, 4, 0x0, 0x264, 0),
127 FH(CLK_APMIXED_VENCPLL, FH_VENCPLL, 0xb0),
Dclk-mt6735-apmixedsys.c74 …PLL(CLK_APMIXED_VENCPLL, "vencpll", VENCPLL_CON0, VENCPLL_PWR_CON0, 0x00000001, CON0_RST_BAR, VENC…
Dclk-mt2712-apmixedsys.c86 PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000100,
/linux-6.14.4/arch/arm64/boot/dts/mediatek/
Dmt8173.dtsi1410 <&apmixedsys CLK_APMIXED_VENCPLL>,
1425 <&apmixedsys CLK_APMIXED_VENCPLL>;