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/linux-6.14.4/Documentation/devicetree/bindings/dma/
Dmediatek,uart-dma.yaml7 title: MediaTek UART APDMA controller
13 The MediaTek UART APDMA controller provides DMA capabilities
38 TX, RX interrupt lines for each UART APDMA channel
43 description: Must contain one entry for the APDMA main clock
47 const: apdma
52 The first cell specifies the UART APDMA channel number
56 Number of virtual channels of the UART APDMA controller
61 description: Enable 33-bits UART APDMA support
89 apdma: dma-controller@11000400 {
118 clock-names = "apdma";
/linux-6.14.4/arch/arm64/boot/dts/mediatek/
Dmt8516.dtsi289 apdma: dma-controller@11000480 { label
306 clock-names = "apdma";
318 dmas = <&apdma 0
319 &apdma 1>;
332 dmas = <&apdma 2
333 &apdma 3>;
346 dmas = <&apdma 4
347 &apdma 5>;
Dmt2712e.dtsi303 dmas = <&apdma 10
304 &apdma 11>;
383 apdma: dma-controller@11000400 { label
412 clock-names = "apdma";
432 dmas = <&apdma 0
433 &apdma 1>;
445 dmas = <&apdma 2
446 &apdma 3>;
458 dmas = <&apdma 4
459 &apdma 5>;
[all …]
Dmt6795.dtsi532 dmas = <&apdma 0>, <&apdma 1>;
544 dmas = <&apdma 2>, <&apdma 3>;
549 apdma: dma-controller@11000380 { label
570 clock-names = "apdma";
582 dmas = <&apdma 4>, <&apdma 5>;
594 dmas = <&apdma 6>, <&apdma 7>;
Dmt8365.dtsi497 apdma: dma-controller@11000280 { label
513 clock-names = "apdma";
523 dmas = <&apdma 0>, <&apdma 1>;
534 dmas = <&apdma 2>, <&apdma 3>;
545 dmas = <&apdma 4>, <&apdma 5>;
/linux-6.14.4/Documentation/devicetree/bindings/spi/
Dsprd,sc9860-spi.yaml67 dmas = <&apdma 11 11>, <&apdma 12 12>;
/linux-6.14.4/drivers/dma/mediatek/
DMakefile2 obj-$(CONFIG_MTK_UART_APDMA) += mtk-uart-apdma.o
DKconfig30 tristate "MediaTek SoCs APDMA support for UART"
Dmtk-uart-apdma.c3 * MediaTek UART APDMA driver.
650 MODULE_DESCRIPTION("MediaTek UART APDMA Controller Driver");
/linux-6.14.4/drivers/clk/mediatek/
Dclk-mt6735-pericfg.c42 GATE_MTK(CLK_PERI_APDMA, "apdma", "axi_sel", &peri_cg_regs, 12, &mtk_clk_gate_ops_setclr),
Dclk-mt8516.c550 GATE_TOP1(CLK_TOP_APDMA, "apdma", "ahb_infra_sel", 2),
Dclk-mt8167.c759 GATE_TOP1(CLK_TOP_APDMA, "apdma", "ahb_infra_sel", 2),